Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 Pin Description and Configuration
- 3.0 Functional Description
- 3.1 10BASE-T/100BASE-TX Transceiver
- 3.2 RMII Interface
- 3.3 Back-to-Back Mode – 100 Mbps Copper Repeater
- 3.4 MII Management (MIIM) Interface
- 3.5 Interrupt (INTRP)
- 3.6 HP Auto MDI/MDI-X
- 3.7 Loopback Mode
- 3.8 LinkMD® Cable Diagnostic
- 3.9 NAND Tree Support
- 3.10 Power Management
- 3.11 Reference Circuit for Power and Ground Connections
- 3.12 Typical Current/Power Consumption
- 4.0 Register Descriptions
- 5.0 Operational Characteristics
- 6.0 Electrical Characteristics
- 7.0 Timing Diagrams
- 8.0 Reset Circuit
- 9.0 Reference Circuits — LED Strap-In Pins
- 10.0 Reference Clock - Connection and Selection
- 11.0 Magnetic - Connection and Selection
- 12.0 Package Outline
2016 Microchip Technology Inc. DS00002199A-page 9
KSZ8081RNA/RND
The PHYAD[1:0] strap-in pin is latched at the de-assertion of reset. In some systems, the RMII MAC receive input pins
may drive high/low during power-up or reset, and consequently cause the PHYAD[1:0] strap-in pin, a shared pin with
the RMII CRS_DV signal, to be latched to the unintended high/low state. In this case an external pull-up (4.7 k) or pull-
down (1.0 k) should be added on the PHYAD[1:0] strap-in pin to ensure that the intended value is strapped-in correctly.
Note 2-4 Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
TABLE 2-2: STRAP-IN OPTIONS - KSZ8081RNA/RND
Pin Number Pin Name
Type
Note 2-4
Description
15 PHYAD[1:0] Ipd/O
The PHY Address is latched at the de-assertion of reset and is con-
figurable to either one of the following two values:
Pull-up = PHY Address is set to 00011b (0x3h)
Pull-down (default) = PHY Address is set to 00000b (0x0h)
PHY Address Bits [4:2] are set to 000 by default.
23 ANEN_SPEED Ipu/O
Auto-Negotiation Enable and SPEED Mode
Pull-up (default) = Enable Auto-Negotiation and set 100 Mbps Speed
Pull-down = Disable Auto-Negotiation and set 10 Mbps Speed
At the de-assertion of reset, this pin value is latched into Register 0h
Bit [12] for Auto-negotiation enable/disable, Register 0h Bit [13] for
the speed select, and Register 4h (Auto-Negotiation Advertisement)
for the speed capability support.