Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 Pin Description and Configuration
- 3.0 Functional Description
- 3.1 10BASE-T/100BASE-TX Transceiver
- 3.2 RMII Interface
- 3.3 Back-to-Back Mode – 100 Mbps Copper Repeater
- 3.4 MII Management (MIIM) Interface
- 3.5 Interrupt (INTRP)
- 3.6 HP Auto MDI/MDI-X
- 3.7 Loopback Mode
- 3.8 LinkMD® Cable Diagnostic
- 3.9 NAND Tree Support
- 3.10 Power Management
- 3.11 Reference Circuit for Power and Ground Connections
- 3.12 Typical Current/Power Consumption
- 4.0 Register Descriptions
- 5.0 Operational Characteristics
- 6.0 Electrical Characteristics
- 7.0 Timing Diagrams
- 8.0 Reset Circuit
- 9.0 Reference Circuits — LED Strap-In Pins
- 10.0 Reference Clock - Connection and Selection
- 11.0 Magnetic - Connection and Selection
- 12.0 Package Outline
KSZ8081RNA/RND
DS00002199A-page 8 2016 Microchip Technology Inc.
Note 2-1 P = power supply
GND = ground
I = input
O = output
I/O = bi-directional
Ipu = Input with internal pull-up (see Section 6.0, "Electrical Characteristics" for value).
Ipu/O = Input with internal pull-up (see Section 6.0, "Electrical Characteristics" for value) during
power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal
pull-up (see Electrical Characteristics for value).
Note 2-2 RMII RX Mode: The RXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each
clock period in which CRS_DV is asserted, two bits of recovered data are sent by the PHY to the
MAC.
Note 2-3 RMII TX Mode: The TXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each
clock period in which TXEN is asserted, two bits of data are received by the PHY from the MAC.
Paddle GND GND Ground.
TABLE 2-1: SIGNALS - KSZ8081RNA/RND (CONTINUED)
Pin
Number
Pin
Name
Type
Note
2-1
Description