Datasheet

 2016 Microchip Technology Inc. DS00002199A-page 7
KSZ8081RNA/RND
16 REF_CLK Ipd/O
RMII – 25 MHz Mode: This pin provides the 50 MHz RMII reference clock out-
put to the MAC.
RMII – 50 MHz Mode: This pin is a no connect.
For unmanaged mode (power-up default setting),
– KSZ8081RNA is in RMII – 25 MHz mode and outputs the 50 MHz RMII ref-
erence clock on this pin.
– KSZ8081RND is in RMII – 50 MHz mode and does not use this pin.
After power-up, both KSZ8081RNA and KSZ8081RND can be programmed
to either 25 MHz mode or 50 MHz mode using PHY Register 1Fh Bit [7].
See also XI (Pin 8).
17 RXER Ipd/O
RMII Receive Error Output.
At the de-assertion of reset, this pin needs to latch in a pull-down value for
normal operation. If MAC side pulls this pin high, see Register 16h, Bit [15] for
solution. It is better having an external pull-down resistor to avoid MAC side
pulls this pin high.
18 INTRP
Ipu/
Opu
Interrupt Output: Programmable interrupt output. This pin has a weak pull-up,
is open drain, and requires an external 1.0 k pull-up resistor.
19 TXEN I RMII Transmit Enable Input.
20 TXD0 I RMII Transmit Data Input [0] (Note 2-3).
21 TXD1 I/O
RMII Transmit Data Input [1] (Note 2-3).
NAND Tree Mode: NAND Tree output pin.
22 GND GND Ground.
23
LED0/
ANEN_SPEED
Ipu/O
LED Output: Programmable LED0 Output.
Config. Mode: Latched as auto-negotiation enable (Register 0h, Bit [12]) and
Speed (Register 0h, Bit [13]) at the de-assertion of reset. See the Strapping
Options section for details.
The LED0 pin is programmable using Register 1Fh bits [5:4], and is defined
as follows:
LED Mode = [00]
Link/Activity Pin State LED Definition
No Link High OFF
Link Low ON
Activity Toggle Blinking
LED Mode = [01]
Link
Pin State LED Definition
No Link High OFF
Link Low ON
LED Mode = [10], [11]: Reserved
24 RST# Ipu Chip Reset (active-low).
TABLE 2-1: SIGNALS - KSZ8081RNA/RND (CONTINUED)
Pin
Number
Pin
Name
Type
Note
2-1
Description