Datasheet

KSZ8081RNA/RND
DS00002199A-page 6  2016 Microchip Technology Inc.
TABLE 2-1: SIGNALS - KSZ8081RNA/RND
Pin
Number
Pin
Name
Type
Note
2-1
Description
1 VDD_1.2 P
1.2V Core V
DD
(power supplied by KSZ8081RNA/KSZ8081RND). Decouple
with 2.2 µF and 0.1 µF capacitors to ground.
2 VDDA_3.3 P 3.3V Analog V
DD
.
3RXMI/O
Physical Receive or Transmit Signal (– differential).
4RXPI/O
Physical Receive or Transmit Signal (+ differential).
5TXMI/O
Physical Transmit or Receive Signal (– differential).
6TXPI/O
Physical Transmit or Receive Signal (+ differential).
7XOO
Crystal Feedback for 25 MHz Crystal. This pin is a no connect if an oscillator
or external clock source is used.
8XII
RMII – 25 MHz Mode: 25 MHz ±50 ppm Crystal/Oscillator/External Clock
Input
RMII – 50 MHz Mode: 50 MHz ±50 ppm Oscillator/External Clock Input
For unmanaged mode (power-up default setting):
– KSZ8081RNA takes in the 25 MHz crystal/clock on this pin.
– KSZ8081RND takes in the 50 MHz clock on this pin.
After power-up, both the KSZ8081RNA and KSZ8081RND can be pro-
grammed to either the 25 MHz mode or 50 MHz mode using PHY Register
1Fh Bit [7].
See also REF_CLK (Pin 16).
9 REXT I
Set PHY Transmit Output Current. Connect a 6.49 k resistor to ground on
this pin.
10 MDIO
Ipu/
Opu
Management Interface (MII) Data I/O. This pin has a weak pull-up, is open-
drain, and requires an external 1.0 k pull-up resistor.
11 MDC Ipu
Management Interface (MII) Clock Input. This clock pin is synchronous to the
MDIO data pin.
12 RXD1 Ipd/O RMII Receive Data Output[1] (Note 2-2).
13 RXD0 Ipu/O
RMII Receive Data Output[0] (Note 2-2).
14 VDDIO P
3.3V, 2.5V, or 1.8V Digital V
DD
.
15
CRS_DV/
PHYAD[1:0]
Ipd/O
RMII Mode: Carrier Sense/Receive Data Valid Output.
Config. Mode: The pull-up/pull-down value is latched as PHYAD[1:0] at the
de-assertion of reset.
See the Strapping Options section for details.