Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 Pin Description and Configuration
- 3.0 Functional Description
- 3.1 10BASE-T/100BASE-TX Transceiver
- 3.2 RMII Interface
- 3.3 Back-to-Back Mode – 100 Mbps Copper Repeater
- 3.4 MII Management (MIIM) Interface
- 3.5 Interrupt (INTRP)
- 3.6 HP Auto MDI/MDI-X
- 3.7 Loopback Mode
- 3.8 LinkMD® Cable Diagnostic
- 3.9 NAND Tree Support
- 3.10 Power Management
- 3.11 Reference Circuit for Power and Ground Connections
- 3.12 Typical Current/Power Consumption
- 4.0 Register Descriptions
- 5.0 Operational Characteristics
- 6.0 Electrical Characteristics
- 7.0 Timing Diagrams
- 8.0 Reset Circuit
- 9.0 Reference Circuits — LED Strap-In Pins
- 10.0 Reference Clock - Connection and Selection
- 11.0 Magnetic - Connection and Selection
- 12.0 Package Outline
2016 Microchip Technology Inc. DS00002199A-page 39
KSZ8081RNA/RND
7.2 Auto-Negotiation Timing
FIGURE 7-3: AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING
TABLE 7-3: AUTO-NEGOTIATION FAST LINK PULSE TIMING PARAMETERS
Parameter Description Min. Typ. Max. Units
t
BTB
FLP burst to FLP burst 8 16 24 ms
t
FLPW
FLP burst width — 2 — ms
t
PW
Clock/Data pulse width — 100 — ns
t
CTD
Clock pulse to data pulse 55.5 64 69.5 µs
t
CTC
Clock pulse to clock pulse 111 128 139 µs
— Number of clock/data pulses per FLP burst 17 — 33 —
AUTO -NEGOTIATION
FAST LINK PULSE (FLP) TIMING
t
PW
TX+/TX-
CLOCK
PULSE
DATA
PULSE
CLOCK
PULSE
t
PW
t
CTD
t
CTC
t
FLPW
t
BTB
TX+/TX-
DATA
PULSE
FLP
BURST
FLP
BURST