Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 Pin Description and Configuration
- 3.0 Functional Description
- 3.1 10BASE-T/100BASE-TX Transceiver
- 3.2 RMII Interface
- 3.3 Back-to-Back Mode – 100 Mbps Copper Repeater
- 3.4 MII Management (MIIM) Interface
- 3.5 Interrupt (INTRP)
- 3.6 HP Auto MDI/MDI-X
- 3.7 Loopback Mode
- 3.8 LinkMD® Cable Diagnostic
- 3.9 NAND Tree Support
- 3.10 Power Management
- 3.11 Reference Circuit for Power and Ground Connections
- 3.12 Typical Current/Power Consumption
- 4.0 Register Descriptions
- 5.0 Operational Characteristics
- 6.0 Electrical Characteristics
- 7.0 Timing Diagrams
- 8.0 Reset Circuit
- 9.0 Reference Circuits — LED Strap-In Pins
- 10.0 Reference Clock - Connection and Selection
- 11.0 Magnetic - Connection and Selection
- 12.0 Package Outline

2016 Microchip Technology Inc. DS00002199A-page 31
KSZ8081RNA/RND
16.8:7 Reserved Reserved RW 0_0
16.6 RMII B-to-B
Override
1 = Override strap-in for RMII back-to-back mode
(also set Bit 1 of this register to ‘1’)
RW 0
16.5 NAND Tree
Override
1 = Override strap-in for NAND tree mode RW 0
16.4:2 Reserved Reserved RW 0_00
16.1 RMII Over-
ride
1 = Override strap-in for RMII mode RW 1
16.0 Reserved Reserved RW 0
Register 17h - Operation Mode Strap Status
17.15:13 PHYAD[2:0]
Strap-In Sta-
tus
[000] = Strap to PHY Address 0
[011] = Strap to PHY Address 3
The KSZ8081RNA/RND supports only PHY
addresses 0h and 3h.
RO
17.12:2 Reserved Reserved RO
17.1 RMII Strap-In
Status
1 = Strap to RMII mode RO
17.0 Reserved Reserved RO
Register 18h - Expanded Control
18.15:12 Reserved Reserved RW 0000
18.11 EDPD Dis-
abled
Energy-detect power-down mode
1 = Disable
0 = Enable
See also Register 10h, Bit [4] for PLL off.
RW 1
18.10:0 Reserved Reserved RW 000_0000_0000
Register 1Bh – Interrupt Control/Status
1B.15 Jabber Inter-
rupt Enable
1 = Enable jabber interrupt
0 = Disable jabber interrupt
RW 0
1B.14 Receive
Error Inter-
rupt Enable
1 = Enable receive error interrupt
0 = Disable receive error interrupt
RW 0
1B.13 Page
Received
Interrupt
Enable
1 = Enable page received interrupt
0 = Disable page received interrupt
RW 0
1B.12 Parallel
Detect Fault
Interrupt
Enable
1 = Enable parallel detect fault interrupt
0 = Disable parallel detect fault interrupt
RW 0
1B.11 Link Partner
Acknowl-
edge Inter-
rupt Enable
1 = Enable link partner acknowledge interrupt
0 = Disable link partner acknowledge interrupt
RW 0
1B.10 Link-Down
Interrupt
Enable
1= Enable link-down interrupt
0 = Disable link-down interrupt
RW 0
1B.9 Remote Fault
Interrupt
Enable
1 = Enable remote fault interrupt
0 = Disable remote fault interrupt
RW 0
TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED)
Address Name Description
Mode
Note 4-1
Default