Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 Pin Description and Configuration
- 3.0 Functional Description
- 3.1 10BASE-T/100BASE-TX Transceiver
- 3.2 RMII Interface
- 3.3 Back-to-Back Mode – 100 Mbps Copper Repeater
- 3.4 MII Management (MIIM) Interface
- 3.5 Interrupt (INTRP)
- 3.6 HP Auto MDI/MDI-X
- 3.7 Loopback Mode
- 3.8 LinkMD® Cable Diagnostic
- 3.9 NAND Tree Support
- 3.10 Power Management
- 3.11 Reference Circuit for Power and Ground Connections
- 3.12 Typical Current/Power Consumption
- 4.0 Register Descriptions
- 5.0 Operational Characteristics
- 6.0 Electrical Characteristics
- 7.0 Timing Diagrams
- 8.0 Reset Circuit
- 9.0 Reference Circuits — LED Strap-In Pins
- 10.0 Reference Clock - Connection and Selection
- 11.0 Magnetic - Connection and Selection
- 12.0 Package Outline
KSZ8081RNA/RND
DS00002199A-page 24 2016 Microchip Technology Inc.
3.12 Typical Current/Power Consumption
Table 3-7, Table 3-8, and Ta b l e 3 - 9 show typical values for current consumption by the transceiver (VDDA_3.3) and dig-
ital I/O (VDDIO) power pins and typical values for power consumption by the KSZ8081RNA/RND device for the indi-
cated nominal operating voltage combinations. These current and power consumption values include the transmit driver
current and on-chip regulator current for the 1.2V core.
TABLE 3-6: KSZ8081RNA/RND POWER PIN DESCRIPTION
Power Pin Pin Number Description
VDD_1.2 1 Decouple with 2.2 µF and 0.1 µF capacitors to ground.
VDDA_3.3 2 Connect to board’s 3.3V supply through a ferrite bead. Decouple with
22 µF and 0.1 µF capacitors to ground.
VDDIO 14 Connect to board’s 3.3V supply for 3.3V VDDIO. Decouple with 22 µF
and 0.1 µF capacitors to ground.
TABLE 3-7: TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 3.3V)
Condition
3.3V Transceiver
(VDDA_3.3)
3.3V Digital I/Os
(VDDIO)
Total Chip Power
100BASE-TX Link-up (no traffic) 34 mA 12 mA 152 mW
100BASE-TX Full-duplex @ 100% utilization 34 mA 13 mA 155 mW
10BASE-T Link-up (no traffic) 14 mA 11 mA 82.5 mW
10BASE-T Full-duplex @ 100% utilization 30 mA 11 mA 135 mW
Power-saving mode (Reg. 1Fh, Bit [10] = 1) 14 mA 10 mA 79.2 mW
EDPD mode (Reg. 18h, Bit [11] = 0) 10 mA 10 mA 66 mW
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1)
3.77 mA 1.54 mA 1.75 mW
Software power-down mode (Reg. 0h, Bit [11] =1) 2.59 mA 1.51 mA 13.5 mW
Software power-down mode (Reg. 0h, Bit [11] =1)
and slow-oscillator mode (Reg. 11h, Bit [5] =1)
1.36 mA 0.45 mA 5.97 mW
TABLE 3-8: TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 2.5V)
Condition
3.3V Transceiver
(VDDA_3.3)
2.5V Digital I/Os
(VDDIO)
Total Chip Power
100BASE-TX Link-up (no traffic) 34 mA 12 mA 142 mW
100BASE-TX Full-duplex @ 100% utilization 34 mA 13 mA 145 mW
10BASE-T Link-up (no traffic) 15 mA 11 mA 77 mW
10BASE-T Full-duplex @ 100% utilization 27 mA 11 mA 117 mW
Power-saving mode (Reg. 1Fh, Bit [10] = 1) 15 mA 10 mA 74.5 mW
EDPD mode (Reg. 18h, Bit [11] = 0) 11 mA 10 mA 61.3 mW
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1)
3.55 mA 1.35 mA 15.1 mW
Software power-down mode (Reg. 0h, Bit [11] =1) 2.29 mA 1.34 mA 10.9 mW
Software power-down mode (Reg. 0h, Bit [11] =1)
and slow-oscillator mode (Reg. 11h, Bit [5] =1)
1.15 mA 0.29 mA 4.52 mW