Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 Pin Description and Configuration
- 3.0 Functional Description
- 3.1 10BASE-T/100BASE-TX Transceiver
- 3.2 RMII Interface
- 3.3 Back-to-Back Mode – 100 Mbps Copper Repeater
- 3.4 MII Management (MIIM) Interface
- 3.5 Interrupt (INTRP)
- 3.6 HP Auto MDI/MDI-X
- 3.7 Loopback Mode
- 3.8 LinkMD® Cable Diagnostic
- 3.9 NAND Tree Support
- 3.10 Power Management
- 3.11 Reference Circuit for Power and Ground Connections
- 3.12 Typical Current/Power Consumption
- 4.0 Register Descriptions
- 5.0 Operational Characteristics
- 6.0 Electrical Characteristics
- 7.0 Timing Diagrams
- 8.0 Reset Circuit
- 9.0 Reference Circuits — LED Strap-In Pins
- 10.0 Reference Clock - Connection and Selection
- 11.0 Magnetic - Connection and Selection
- 12.0 Package Outline

KSZ8081RNA/RND
DS00002199A-page 22 2016 Microchip Technology Inc.
3.9.1 NAND TREE I/O TESTING
Use the following procedure to check for faults on the KSZ8081RNA/RND digital I/O pin connections to the board:
1. Enable NAND tree mode by setting Register 16h, Bit [5] to ‘1’.
2. Use board logic to drive all KSZ8081RNA/RND NAND tree input pins high.
3. Use board logic to drive each NAND tree input pin, in KSZ8081RNA/RND tree pin order, as follows:
a) Toggle the first pin (MDIO) from high to low, and verify that the TDX1 pin switches from high to low to indicate
that the first pin is connected properly.
b) Leave the first pin (MDIO) low.
c) Toggle the second pin (MDC) from high to low, and verify that the TXD1 pin switches from low to high to
indicate that the second pin is connected properly.
d) Leave the first pin (MDIO) and the second pin (MDC) low.
e) Toggle the third pin from high to low, and verify that the TXD1 pin switches from high-to-low to indicate that
the third pin is connected properly.
f) Continue with this sequence until all KSZ8081RNA/RND NAND tree input pins have been toggled.
Each KSZ8081RNA/RND NAND tree input pin must cause the TXD1 output pin to toggle high-to-low or low-to-high to
indicate a good connection. If the TXD1 pin fails to toggle when the KSZ8081RNA/RND input pin toggles from high to
low, the input pin has a fault.
3.10 Power Management
The KSZ8081RNA/RND incorporates a number of power-management modes and features that provide methods to
consume less energy. These are discussed in the following sections.
3.10.1 POWER-SAVING MODE
Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled
by writing a ‘1’ to Register 1Fh, Bit [10], and is in effect when auto-negotiation mode is enabled and the cable is discon-
nected (no link).
In this mode, the KSZ8081RNA/RND shuts down all transceiver blocks except the transmitter, energy detect, and PLL
circuits.
By default, power-saving mode is disabled after power-up.
3.10.2 ENERGY-DETECT POWER-DOWN MODE
Energy-detect power-down (EDPD) mode is used to further reduce transceiver power consumption when the cable is
unplugged. It is enabled by writing a ‘0’ to Register 18h, Bit [11], and is in effect when auto-negotiation mode is enabled
and the cable is disconnected (no link).
EDPD mode works with the PLL off (set by writing a ‘1’ to Register 10h, Bit [4] to automatically turn the PLL off in EDPD
mode) to turn off all KSZ8081RNA/RND transceiver blocks except the transmitter and energy-detect circuits.
TABLE 3-5: NAND TREE TEST PIN ORDER FOR KSZ8081RNA/RND
Pin Number Pin Name NAND Tree Description
10 MDIO Input
11 MDC Input
12 RXD1 Input
13 RXD0 Input
15 CRS_DV Input
16 REF_CLK Input
18 INTRP Input
19 TXEN Input
23 LED0 Input
20 TXD0 Input
21 TXD1 Output