Datasheet

KSZ8081RNA/RND
DS00002199A-page 14  2016 Microchip Technology Inc.
3.2.1.6 Receive Error (RXER)
RXER is asserted for one or more REF_CLK periods to indicate that a symbol error (for example, a coding error that a
PHY can detect that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame being
transferred from the PHY.
RXER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RXER has no effect on the
MAC.
3.2.1.7 Collision Detection (COL)
The MAC regenerates the COL signal of the MII from TXEN and CRS_DV.
3.2.2 RMII SIGNAL DIAGRAM – 25/50 MHZ CLOCK MODE
The KSZ8081RNA/RND RMII pin connections to the MAC for 25 MHz clock mode are shown in Figure 3-2. The con-
nections for 50 MHz clock mode are shown in Figure 3-3.
3.2.2.1 RMII – 25 MHz Clock Mode
The KSZ8081RNA is configured to RMII – 25 MHz clock mode after it is powered up or hardware reset with the following:
• A 25 MHz crystal connected to XI, XO (Pins 8, 7), or an external 25 MHz clock source (oscillator) connected to XI
The KSZ8081RND can optionally be configured to RMII – 25 MHz clock mode after it is powered up or hardware reset
and software programmed with the following:
• A 25 MHz crystal connected to XI, XO (Pins 8, 7), or an external 25 MHz clock source (oscillator) connected to XI
• Register 1Fh, Bit [7] programmed to ‘1’ to select RMII – 25 MHz clock mode
FIGURE 3-2: KSZ8081RNA/RND RMII INTERFACE (RMII - 25 MHZ CLOCK MODE)
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KSZ8081RNA/RND
CRS_DV
RXD[1:0]
RXER
TXD[1:0]
RMII MAC
CRS_DV
RXD[1:0]
TXD[1:0]
RX_ER
REF_CLK
TXEN TX_EN
XI
REF_CLK
XO
25MHz
XTAL
22pF 22pF