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ManualsBrandsMICROCHIP TECHNOLOGY ManualsInterface ICsInterface IC - transceivers RMII 1/1 QFN 24

Table Of Contents

 2016 Microchip Technology Inc. DS00002199A-page 1

Features

• Single-Chip 10BASE-T/100BASE-TX IEEE 802.3

Compliant Ethernet Transceiver

• RMII v1.2 Interface Support with a 50 MHz Refer-

ence Clock Output to MAC, and an Option to

Input a 50 MHz Reference Clock

• RMII Back-to-Back Mode Support for a 100 Mbps

Copper Repeater

• MDC/MDIO Management Interface for PHY Reg-

ister Configuration

• Programmable Interrupt Output

• LED Outputs for Link and Activity Status Indica-

tion

• On-Chip Termination Resistors for the Differential

Pairs

• Baseline Wander Correction

• HP Auto MDI/MDI-X to Reliably Detect and Cor-

rect Straight-Through and Crossover Cable Con-

nections with Disable and Enable Option

• Auto-Negotiation to Automatically Select the

Highest Link-Up Speed (10/100 Mbps) and

Duplex (Half/Full)

• Power-Down and Power-Saving Modes

• LinkMD

TDR-Based Cable Diagnostics to Iden-

tify Faulty Copper Cabling

• Parametric NAND Tree Support for Fault Detec-

tion Between Chip I/Os and the Board

• HBM ESD Rating (6 kV)

• Loopback Modes for Diagnostics

• Single 3.3V Power Supply with V

I/O Options

for 1.8V, 2.5V, or 3.3V

• Built-In 1.2V Regulator for Core

• Available in 24-pin 4 mm x 4 mm QFN Package

Target Applications

• Game Consoles

• IP Phones

• IP Set-Top Boxes

•IP TVs

•LOM

• Printers

KSZ8081RNA/RND

10BASE-T/100BASE-TX PHY with RMII

Support

Summary of content (52 pages)

PAGE 1
KSZ8081RNA/RND 10BASE-T/100BASE-TX PHY with RMII Support Features Target Applications • Single-Chip 10BASE-T/100BASE-TX IEEE 802.3 Compliant Ethernet Transceiver • RMII v1.
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KSZ8081RNA/RND TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.
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KSZ8081RNA/RND Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 4 2.0 Pin Description and Configuration .................................................................................................................................................. 5 3.0 Functional Description ................................................................
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KSZ8081RNA/RND 1.0 INTRODUCTION 1.1 General Description The KSZ8081RNA/RND is a single-supply 10BASE-T/100BASE-TX Ethernet physical-layer transceiver for transmission and reception of data over standard CAT-5 unshielded twisted pair (UTP) cable. The KSZ8081RNA/RND is a highly-integrated PHY solution. It reduces board cost and simplifies board layout by using on-chip termination resistors for the differential pairs and by integrating a low-noise regulator to supply the 1.2V core, and by offering 1.8/2.
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KSZ8081RNA/RND PIN DESCRIPTION AND CONFIGURATION TXEN 22 TXD0 23 TXD1 24 GND 24-QFN PIN ASSIGNMENT (TOP VIEW) LED0 / ANEN_SPEED FIGURE 2-1: RST# 21 20 19 VDD_1.2 1 18 INTRP VDDA_3.3 2 17 RXER RXM 3 16 REF_CLK PADDLE GROUND (ON BOTTOM OF CHIP) RXP 4 15 CRS_DV/ PHYAD[1:0] TXP 6 13 RXD0  2016 Microchip Technology Inc. 9 10 MDIO 8 REXT XO 7 11 12 RXD1 14 VDDIO MDC TXM 5 XI 2.
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KSZ8081RNA/RND TABLE 2-1: SIGNALS - KSZ8081RNA/RND Pin Number Pin Name Type Note 2-1 Description 1 VDD_1.2 P 1.2V Core VDD (power supplied by KSZ8081RNA/KSZ8081RND). Decouple with 2.2 µF and 0.1 µF capacitors to ground. 2 VDDA_3.3 P 3.3V Analog VDD. 3 RXM I/O Physical Receive or Transmit Signal (– differential). 4 RXP I/O Physical Receive or Transmit Signal (+ differential). 5 TXM I/O Physical Transmit or Receive Signal (– differential).
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KSZ8081RNA/RND TABLE 2-1: Pin Number 16 SIGNALS - KSZ8081RNA/RND (CONTINUED) Type Note 2-1 Pin Name REF_CLK Ipd/O Description RMII – 25 MHz Mode: This pin provides the 50 MHz RMII reference clock output to the MAC. RMII – 50 MHz Mode: This pin is a no connect. For unmanaged mode (power-up default setting), – KSZ8081RNA is in RMII – 25 MHz mode and outputs the 50 MHz RMII reference clock on this pin. – KSZ8081RND is in RMII – 50 MHz mode and does not use this pin.
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KSZ8081RNA/RND TABLE 2-1: SIGNALS - KSZ8081RNA/RND (CONTINUED) Pin Number Pin Name Type Note 2-1 Paddle GND GND Description Ground. Note 2-1 P = power supply GND = ground I = input O = output I/O = bi-directional Ipu = Input with internal pull-up (see Section 6.0, "Electrical Characteristics" for value). Ipu/O = Input with internal pull-up (see Section 6.0, "Electrical Characteristics" for value) during power-up/reset; output pin otherwise.
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KSZ8081RNA/RND The PHYAD[1:0] strap-in pin is latched at the de-assertion of reset. In some systems, the RMII MAC receive input pins may drive high/low during power-up or reset, and consequently cause the PHYAD[1:0] strap-in pin, a shared pin with the RMII CRS_DV signal, to be latched to the unintended high/low state. In this case an external pull-up (4.7 kΩ) or pulldown (1.0 kΩ) should be added on the PHYAD[1:0] strap-in pin to ensure that the intended value is strapped-in correctly.
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KSZ8081RNA/RND 3.0 FUNCTIONAL DESCRIPTION The KSZ8081RNA is an integrated, single 3.3V supply, fast Ethernet transceiver. It is fully compliant with the IEEE 802.3 Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two differential pairs and by integrating the regulator to supply the 1.2V core.
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KSZ8081RNA/RND 3.1.5 10BASE-T RECEIVE On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV, or with short pulse widths, to prevent noise at the RXP and RXM inputs from falsely triggering the decoder.
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KSZ8081RNA/RND FIGURE 3-1: AUTO-NEGOTIATION FLOW CHART START AUTO-NEGOTIATION FORCE LINK SETTING NO PARALLEL OPERATION YES BYPASS AUTO-NEGOTIATION AND SET LINK MODE ATTEMPT AUTONEGOTIATION LISTEN FOR 100BASE-TX IDLES LISTEN FOR 10BASE-T LINK PULSES NO JOIN FLOW LINK MODE SET? YES LINK MODE SET 3.2 RMII Interface The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII).
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KSZ8081RNA/RND TABLE 3-1: RMII SIGNAL DEFINITION RMII Signal Name Direction with Respect to PHY, KSZ8081 Signal REF_CLK Output (25 MHz Clock Mode)/ No Connect (50 MHz Clock Mode) Direction with Respect to MAC Description Input/ Synchronous 50 MHz reference clock for receive, transInput or No Connect mit, and control interface TXEN Input Output Transmit Enable TXD[1:0] Input Output Transmit Data[1:0] CRS_DV Output Input Carrier Sense/Receive Data Valid RXD[1:0] Output Input Receive Da
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KSZ8081RNA/RND 3.2.1.6 Receive Error (RXER) RXER is asserted for one or more REF_CLK periods to indicate that a symbol error (for example, a coding error that a PHY can detect that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame being transferred from the PHY. RXER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RXER has no effect on the MAC. 3.2.1.
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KSZ8081RNA/RND 3.2.2.
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KSZ8081RNA/RND 3.3 Back-to-Back Mode – 100 Mbps Copper Repeater Two KSZ8081RNA/RND devices can be connected back-to-back to form a managed 100BASE-TX copper repeater. FIGURE 3-4: KSZ8081RNA/RND AND KSZ8081RNA/RND RMII BACK-TO-BACK COPPER REPEATER RxD RXP/RXM TXP/TXM KSZ8081RNA/RND (COPPER MODE) TxD XI 50MHz OSC XI TXP/TXM KSZ8081RNA/RND (COPPER MODE) RxD RXP/RXM 3.3.
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KSZ8081RNA/RND 3.4 MII Management (MIIM) Interface The KSZ8081RNA/RND supports the IEEE 802.3 MII management interface, also known as the Management Data Input/Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and control the state of the KSZ8081RNA/RND. An external device with MIIM capability is used to read the PHY status and/ or configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.
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KSZ8081RNA/RND TABLE 3-4: MDI/MDI-X PIN DESCRIPTION MDI 3.6.1 MDI-X RJ-45 Pin Signal RJ-45 Pin Signal 1 2 TX+ 1 RX+ TX– 2 RX– 3 6 RX+ 3 TX+ RX– 6 TX– STRAIGHT CABLE A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-5 shows a typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device).
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KSZ8081RNA/RND FIGURE 3-6: TYPICAL CROSSOVER CABLE CONNECTION 10/100 ETHERNET MEDIA DEPENDENT INTERFACE 1 RECEIVE PAIR 2 TRANSMIT PAIR 10/100 ETHERNET MEDIA DEPENDENT INTERFACE CROSSOVER CABLE 2 3 3 4 4 5 5 6 6 7 7 8 8 MODULAR CONNECTOR (RJ-45) HUB (REPEATER OR SWITCH) 3.7 1 RECEIVE PAIR TRANSMIT PAIR MODULAR CONNECTOR (RJ-45) HUB (REPEATER OR SWITCH) Loopback Mode The KSZ8081RNA/RND supports the following loopback operations to verify analog and/or digital data paths.
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KSZ8081RNA/RND The following programming action and register settings are used for local loopback mode: For 10/100 Mbps loopback: Set Register 0h, Bit [14] = 1 // Enable local loopback mode Bit [13] = 0/1 // Select 10 Mbps/100 Mbps speed Bit [12] = 0 // Disable auto-negotiation Bit [8] = 1 // Select full-duplex mode Follow the steps below if you don’t want the frames go out from the copper port in the local loopback. 1. 2. 3. Set register 1Fh bit [3] to ‘1’ to disable the transmitter.
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KSZ8081RNA/RND LinkMD® Cable Diagnostic 3.8 The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems. These include open circuits, short circuits, and impedance mismatches. LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the shape of the reflected signal to determine the type of fault.
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KSZ8081RNA/RND TABLE 3-5: 3.9.1 NAND TREE TEST PIN ORDER FOR KSZ8081RNA/RND Pin Number Pin Name NAND Tree Description 10 MDIO Input 11 MDC Input 12 RXD1 Input 13 RXD0 Input 15 CRS_DV Input 16 REF_CLK Input 18 INTRP Input 19 TXEN Input 23 LED0 Input 20 TXD0 Input 21 TXD1 Output NAND TREE I/O TESTING Use the following procedure to check for faults on the KSZ8081RNA/RND digital I/O pin connections to the board: 1. 2. 3.
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KSZ8081RNA/RND Power can be reduced further by extending the time interval between transmissions of link pulses to check for the presence of a link partner. The periodic transmission of link pulses is needed to ensure two link partners in the same low power state and with auto MDI/MDI-X disabled can wake up when the cable is connected between them. By default, energy-detect power-down mode is disabled after power-up. 3.10.
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KSZ8081RNA/RND TABLE 3-6: 3.12 KSZ8081RNA/RND POWER PIN DESCRIPTION Power Pin Pin Number Description VDD_1.2 1 Decouple with 2.2 µF and 0.1 µF capacitors to ground. VDDA_3.3 2 Connect to board’s 3.3V supply through a ferrite bead. Decouple with 22 µF and 0.1 µF capacitors to ground. VDDIO 14 Connect to board’s 3.3V supply for 3.3V VDDIO. Decouple with 22 µF and 0.1 µF capacitors to ground.
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KSZ8081RNA/RND TABLE 3-9: TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 1.8V) Condition 3.3V Transceiver (VDDA_3.3) 1.8V Digital I/Os (VDDIO) 100BASE-TX Link-up (no traffic) 34 mA 11 mA 132 mW 100BASE-TX Full-duplex @ 100% utilization 34 mA 12 mA 134 mW Total Chip Power 10BASE-T Link-up (no traffic) 15 mA 10 mA 67.5 mW 10BASE-T Full-duplex @ 100% utilization 27 mA 10 mA 107 mW Power-saving mode (Reg. 1Fh, Bit [10] = 1) 15 mA 9 mA 65.7 mW EDPD mode (Reg.
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KSZ8081RNA/RND 4.0 REGISTER DESCRIPTIONS This chapter describes the various control and status registers (CSRs). 4.
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KSZ8081RNA/RND TABLE 4-2: Address REGISTER DESCRIPTIONS (CONTINUED) Mode Note 4-1 Name Description 0.12 Auto-Negotiation Enable 1 = Enable auto-negotiation process RW 0 = Disable auto-negotiation process If enabled, the auto-negotiation result overrides the settings in Registers 0.13 and 0.8. 0.11 Power-Down 1 = Power-down mode 0 = Normal operation If software reset (Register 0.15) is used to exit power-down mode (Register 0.11 = 1), two software reset writes (Register 0.15 = 1) are required.
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KSZ8081RNA/RND TABLE 4-2: Address 1.0 REGISTER DESCRIPTIONS (CONTINUED) Name Description Extended Capability 1 = Supports extended capability registers Mode Note 4-1 RO Default 1 Register 2h - PHY Identifier 1 2.15:0 PHY ID Number Assigned to the 3rd through 18th bits of the Organi- RO zationally Unique Identifier (OUI). KENDIN Communication’s OUI is 0010A1 (hex). 0022h Register 3h - PHY Identifier 2 3.
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KSZ8081RNA/RND TABLE 4-2: Address REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Note 4-1 Default 5.14 Acknowledge 1 = Link code word received from partner 0 = Link code word not yet received RO 0 5.13 Remote Fault 1 = Remote fault detected 0 = No remote fault RO 0 5.12 Reserved Reserved RO 0 5.11:10 Pause [00] = No pause [10] = Asymmetric pause [01] = Symmetric pause [11] = Asymmetric and symmetric pause RO 00 5.9 100Base-T4 1 = T4 capable 0 = No T4 capability RO 0 5.
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KSZ8081RNA/RND TABLE 4-2: Address 7.10:0 REGISTER DESCRIPTIONS (CONTINUED) Name Description Message Field 11-bit wide field to encode 2048 messages Mode Note 4-1 Default RW 000_0000_0001 RO 0 Register 8h - Link Partner Next Page Ability 8.15 Next Page 1 = Additional next pages will follow 0 = Last page 8.14 Acknowledge 1 = Successful receipt of link word 0 = No successful receipt of link word RO 0 8.13 Message Page 1 = Message page 0 = Unformatted page RO 0 8.
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KSZ8081RNA/RND TABLE 4-2: Address REGISTER DESCRIPTIONS (CONTINUED) Mode Note 4-1 Name Description Default 16.8:7 Reserved Reserved RW 0_0 16.6 RMII B-to-B Override 1 = Override strap-in for RMII back-to-back mode (also set Bit 1 of this register to ‘1’) RW 0 16.5 NAND Tree Override 1 = Override strap-in for NAND tree mode RW 0 16.4:2 Reserved Reserved RW 0_00 16.1 RMII Override 1 = Override strap-in for RMII mode RW 1 16.
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KSZ8081RNA/RND TABLE 4-2: Address REGISTER DESCRIPTIONS (CONTINUED) Name Description 1B.8 Link-Up Interrupt Enable 1 = Enable link-up interrupt 0 = Disable link-up interrupt 1B.7 Mode Note 4-1 Default RW 0 Jabber Inter- 1 = Jabber occurred rupt 0 = Jabber did not occur RO/SC 0 1B.6 Receive Error Interrupt 1 = Receive error occurred 0 = Receive error did not occur RO/SC 0 1B.5 Page Receive Interrupt 1 = Page receive occurred 0 = Page receive did not occur RO/SC 0 1B.
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KSZ8081RNA/RND TABLE 4-2: Address REGISTER DESCRIPTIONS (CONTINUED) Mode Note 4-1 Name Description Default 1E.5 MDI/MDI-X State 1 = MDI-X 0 = MDI RO 1E.4 Energy Detect 1 = Signal present on receive differential pair 0 = No signal detected on receive differential pair RO 0 1E.3 PHY Isolate 1 = PHY in isolate mode 0 = PHY in normal operation RW 0 1E.
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KSZ8081RNA/RND TABLE 4-2: Address REGISTER DESCRIPTIONS (CONTINUED) Mode Note 4-1 Name Description 1F.2 Remote Loopback 1 = Remote (analog) loopback is enabled 0 = Normal mode RW 0 1F.1 Reserved Reserved RW 0 1F.0 Disable Data 1 = Disable scrambler Scrambling 0 = Enable scrambler RW 0 Note 4-1 Default RW = Read/Write; RO = Read Only; SC = Self-Cleared; LH = Latch High; LL = Latch Low. DS00002199A-page 34  2016 Microchip Technology Inc.
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KSZ8081RNA/RND 5.0 OPERATIONAL CHARACTERISTICS 5.1 Absolute Maximum Ratings* Supply Voltage (VIN) (VDD_1.2).................................................................................................................................................... –0.5V to +1.8V (VDDIO, VDDA_3.3) ...................................................................................................................................... –0.5V to +5.0V Input Voltage (all inputs)...........................................
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KSZ8081RNA/RND 6.0 ELECTRICAL CHARACTERISTICS TA = 25°C. Specification is for packaged product only. TABLE 6-1: ELECTRICAL CHARACTERISTICS Parameters Symbol Min. Typ. Max. Units Note Supply Current (VDDIO, VDDA_3.3 = 3.3V), Note 6-1 10BASE-T IDD1_3.3V — 41 — mA Full-duplex traffic @ 100% utilization 100BASE-TX IDD2_3.3V — 47 — mA Full-duplex traffic @ 100% utilization EDPD Mode IDD3_3.3V — 20 — mA Ethernet cable disconnected (Reg. 18h.11 = 0) Power-Down Mode IDD4_3.
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KSZ8081RNA/RND TABLE 6-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Parameters Symbol Min. Typ. Max. Units Note — — 300 — ps Peak-to-peak. Applies only to RMII 25 MHz Clock Mode. µs Link loss detected at receive differential inputs to PHY signal indication time for each of the following: 1. For LED mode 01, Link LED output changes from low (link-up) to high (link-down). 2. INTRP pin asserts for link-down status change.
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KSZ8081RNA/RND 7.0 TIMING DIAGRAMS 7.1 RMII Timing FIGURE 7-1: RMII TIMING - DATA RECEIVED FROM RMII tCYC TRANSMIT TIMING REF_CLK t1 t2 TXEN TXD[1:0] FIGURE 7-2: RMII TIMING - DATA INPUT TO RMII tCYC RECEIVE TIMING REF_CLK CRS_DV RXD[1:0] RXER tOD TABLE 7-1: RMII TIMING PARAMETERS (25 MHZ INPUT TO XI PIN, 50 MHZ OUTPUT FROM REF_CLK PIN) Parameter Description Min. Typ. Max.
PAGE 39
KSZ8081RNA/RND 7.2 Auto-Negotiation Timing FIGURE 7-3: AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING AUTO -NEGOTIATION FAST LINK PULSE (FLP) TIMING FLP BURST FLP BURST TX+/TXtFLPW tBTB CLOCK PULSE DATA PULSE tPW tPW CLOCK PULSE DATA PULSE TX+/TX- tCTD tCTC TABLE 7-3: AUTO-NEGOTIATION FAST LINK PULSE TIMING PARAMETERS Parameter Description Min. Typ. Max.
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KSZ8081RNA/RND 7.3 MDC/MDIO Timing FIGURE 7-4: MDC/MDIO TIMING tP MDC tMD1 MDIO (PHY INPUT) tMD2 VALID DATA VALID DATA tMD3 MDIO (PHY OUTPUT) TABLE 7-4: VALID DATA MDC/MDIO TIMING PARAMETERS Parameter Description Min. Typ. Max. Units fc MDC Clock Frequency — 2.
PAGE 41
KSZ8081RNA/RND 7.4 Power-Up/Reset Timing The KSZ8081RNA/RND reset timing requirement is summarized in Figure 7-5 and Table 7-5. FIGURE 7-5: POWER-UP/RESET TIMING SUPPLY VOLTAGES tVR tSR RST# tCS tCH STRAP-IN VALUE tRC STRAP-IN / OUTPUT PIN TABLE 7-5: POWER-UP/RESET TIMING PARAMETERS Parameter Description Min. Typ. Max. Units tVR Supply voltage (VDDIO, VDDA_3.3) rise time 300 — — µs tSR Stable supply voltage (VDDIO, VDDA_3.
PAGE 42
KSZ8081RNA/RND 8.0 RESET CIRCUIT Figure 8-1 shows a reset circuit recommended for powering up the KSZ8081RNA/RND if reset is triggered by the power supply. FIGURE 8-1: RECOMMENDED RESET CIRCUIT VDDIO D1: 1N4148 D1 KSZ8081RNA/RND R 10K RST# C 10μF Figure 8-2 shows a reset circuit recommended for applications where reset is driven by another device (for example, the CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset.
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KSZ8081RNA/RND 9.0 REFERENCE CIRCUITS — LED STRAP-IN PINS The pull-up, float, and pull-down reference circuits for the LED0/ANEN_SPEED strapping pin are shown in Figure 9-1 for 3.3V and 2.5V VDDIO. FIGURE 9-1: REFERENCE CIRCUITS FOR LED STRAPPING PINS VDDIO = 3.3V, 2.5V PULL-UP 4.7k 220 KSZ8081RNA/RND LED0 PIN VDDIO = 3.3V, 2.5V FLOAT 220 KSZ8081RNA/RND LED0 PIN VDDIO = 3.3V, 2.5V PULL-DOWN 220 KSZ8081RNA/RND LED0 PIN 1k For 1.
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KSZ8081RNA/RND 10.0 REFERENCE CLOCK - CONNECTION AND SELECTION A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ8081RNA/ RND. For the KSZ8081RNA/RND in RMII – 25 MHz clock mode, the reference clock is 25 MHz. The reference clock connections to XI (Pin 8) and XO (Pin 7), and the reference clock selection criteria, are provided in Figure 10-1 and Table 10-1.
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KSZ8081RNA/RND 11.0 MAGNETIC - CONNECTION AND SELECTION A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs exceeding FCC requirements. The KSZ8081RNA/RND design incorporates voltage-mode transmit drivers and on-chip terminations. With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential pairs.
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KSZ8081RNA/RND TABLE 11-2: COMPATIBLE SINGLE-PORT 10/100 MAGNETICS Manufacturer Part Number Temperature Range Magnetic + RJ-45 Bel Fuse S558-5999-U7 0°C to 70°C No Bel Fuse SI-46001-F 0°C to 70°C Yes Bel Fuse SI-50170-F 0°C to 70°C Yes Delta LF8505 0°C to 70°C No HALO HFJ11-2450E 0°C to 70°C Yes HALO TG110-E055N5 –40°C to 85°C No LANKom LF-H41S-1 0°C to 70°C No Pulse H1102 0°C to 70°C No Pulse H1260 0°C to 70°C No Pulse HX1188 –40°C to 85°C No Pulse J00-0014 0
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KSZ8081RNA/RND 12.0 Note: PACKAGE OUTLINE For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging FIGURE 12-1: 24-LEAD QFN 4 MM X 4 MM PACKAGE  2016 Microchip Technology Inc.
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KSZ8081RNA/RND APPENDIX A: TABLE A-1: DATA SHEET REVISION HISTORY REVISION HISTORY Revision DS00002199A (06-14-16) DS00002199A-page 48 Section/Figure/Entry — Correction Converted Micrel data sheet KSZ8081RNA/RND to Microchip DS00002199A. Minor text changes throughout.  2016 Microchip Technology Inc.
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KSZ8081RNA/RND THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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KSZ8081RNA/RND PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.