Datasheet
2010 Microchip Technology Inc. DS39935C-page 61
ENC424J600/624J600
5.3.5 MODE 5
PSP Mode 5 is an 8-bit, partially multiplexed mode that
is available on all devices. The parallel interface con-
sists of 8 multiplexed address and data pins (AD<7:0>),
plus one required high address bit (AD8) and 6 optional
address-only pins (AD<14:9>).
Selecting PSP Mode 5 differs between 44-pin and
64-pin devices, as shown in Figure 5-13. For the 44-pin
ENC424J600, tie PSPCFG0 to V
SS. For the 64-pin
ENC624J600, tie PSPCFG1 and PSPCFG2 to V
SS,
and PSPCFG3 to V
DD.
This mode uses active-high Read and Write (RD and
WR) strobes, as well as separate Chip Select and
Address Latch (CS and AL) lines. These four pins allow
the host to select the device, latch an address, then
indicate when a read or write operation is desired. For
proper operation, treat the RD, WR and AL strobes as
mutually exclusive whenever the ENCX24J600 is
selected. Only raise one of these to logic high at any
given time.
AD<14:8> are used as address inputs only, and are
therefore, always left in a high-impedance state. When
CS or RD is driven low, the multiplexed AD<7:0> pins
stay in a high-impedance state.
To perform a read operation:
1. Raise CS (if connected to the host).
2. Present the address to read from on AD<14:0>.
3. Strobe the AL pin high and low.
4. Set the host controller’s AD<7:0> bus pins as
inputs.
5. Raise RD.
The AD<7:0> bus begins driving out indeterminate data
for a brief period, then switches to the correct read data
after the appropriate read access time has elapsed.
When RD is lowered, the AD<7:0> pins return to a
high-impedance state.
To perform a write operation:
1. Raise CS (if connected to the host).
2. Present the address to write to on AD<14:0>.
3. Strobe the AL pin.
4. Change the data on AD<7:0> from the lower
address byte to the data to be written.
5. Strobe WR high and then low.
If a subsequent read or write of the same memory
address is desired, it is possible to restrobe RD or WR
without going through another address latch cycle.
Sample timing diagrams for reading and writing data in
this mode are provided in Figure 5-14 and Figure 5-15,
respectively.