Information

ENC28J60
DS80349C-page 2 2010 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature Issue Issue Summary
Affected
Revisions
B1 B4 B5 B7
MAC
Interface
1. MAC registers unreliable with slow asynchronous SPI
clock
XX
Reset 2. CLKRDY set early X X X X
Core Operating
Specifications
3. Industrial (-40C to +85C) temperature range
unsupported
XX
Oscillator CLKOUT pin 4. CLKOUT unavailable in Power Save mode X X X X
Memory Ethernet
Buffer
5. Receive buffer must start at 0000h X X X X
Interrupts 6. Receive Packet Pending Interrupt Flag (PKTIF) unreliable X X X X
PHY 7. TPIN+/- automatic polarity detection and correction
unreliable
XXXX
PHY 8. RBIAS resistor value differs between silicon revisions X X
PHY 9. Internal loopback in half-duplex unreliable X X X X
PHY 10. Internal loopback in full-duplex unreliable X X X X
PHY LEDs 11. Combined Collision and Duplex Status mode unavailable X X X X
Transmit
Logic
12. Transmit abort may stall transmit logic X X X X
PHY 13. Received link pulses potentially cause collisions X X
Memory Ethernet
Buffer
14. Even values in ERXRDPT may corrupt receive buffer X X X X
Transmit
Logic
15. LATECOL Status bit unreliable X X X X
PHY LEDs 16. LED auto-polarity detection unreliable X X X X
DMA 17. DMA checksum calculations will abort receive packets X X X X
Receive
Filter
18. Pattern match filter allows reception of extra packets X X X X
SPI
Interface
19. Reset command unavailable in Power Save mode X X X X
TABLE 3: ETHERNET CONFORMANCE ISSUES
Issue Issue Summary
Affected
Revisions
B1 B4 B5 B7
1. TP_IDL transmit waveform violates IEEE STD 802.3™ template X X
2. PHY accepts receive packet in Link Test Fail state X X
3. Collision enforcement is delayed X X