Datasheet

PIC32MX330/350/370/430/450/470 DS60001185C-page 84  2012-2013 Microchip Technology Inc.
TABLE 4-37: RTCC REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0200 RTCCON
31:16
— — — — — — CAL<9:0> 0000
15:0 ON
—SIDL — — — — — RTSECSEL RTCCLKON — — RTCWREN RTCSYNC HALFSEC RTCOE 0000
0210 RTCALRM
31:16 — — — — — — — — — — — — — — — — 0000
15:0
ALRMEN CHIME PIV ALRMSYNC AMASK<3:0> ARPT<7:0> 0000
0220 RTCTIME
31:16 HR10<3:0> HR01<3:0> MIN10<3:0> MIN01<3:0> xxxx
15:0 SEC10<3:0> SEC01<3:0>
— — — — — — — — xx00
0230 RTCDATE
31:16 YEAR10<3:0> YEAR01<3:0> MONTH10<3:0> MONTH01<3:0> xxxx
15:0 DAY10<3:0> DAY01<3:0>
— — — — WDAY01<3:0> xx00
0240 ALRMTIME
31:16 HR10<3:0> HR01<3:0> MIN10<3:0> MIN01<3:0> xxxx
15:0 SEC10<3:0> SEC01<3:0>
— — — — — — — — xx00
0250 ALRMDATE
31:16 — — — — — — — — MONTH10<3:0> MONTH01<3:0> 00xx
15:0 DAY10<3:0> DAY01<3:0>
— — — — WDAY01<3:0> xx0x
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-38: CTMU REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
A200 CTMUCON
31:16 EDG1MOD EDG1POL
EDG1SEL<3:0>
EDG2STAT
EDG1STAT EDG2MOD EDG2POL EDG2SEL<3:0>
— —
0000
15:0 ON — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG ITRIM<5:0> IRNG<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.