Datasheet

 2012-2013 Microchip Technology Inc. DS60001185C-page 33
PIC32MX330/350/370/430/450/470
3.0 CPU
The the MIPS32
®
M4K
®
Processor Core is the heart of
the PIC32MX330/350/370/430/450/470 device proces
-
sor. The CPU fetches instructions, decodes each
instruction, fetches source operands, executes each
instruction and writes the results of instruction
execution to the proper destinations.
3.1 Features
• 5-stage pipeline
• 32-bit address and data paths
• MIPS32
®
Enhanced Architecture (Release 2):
- Multiply-accumulate and multiply-subtract
instructions
- Targeted multiply instruction
- Zero/One detect instructions
- WAIT instruction
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
for interrupt handlers
- Bit field manipulation instructions
• MIPS16e
®
Code Compression:
- 16-bit encoding of 32-bit instructions to
improve code density
- Special PC-relative instructions for efficient
loading of addresses and constants
- SAVE and RESTORE macro instructions for
setting up and tearing down stack frames
within subroutines
- Improved support for handling 8 and 16-bit
data types
• Simple Fixed Mapping Translation (FMT)
Mechanism:
• Simple Dual Bus Interface:
- Independent 32-bit address and data buses
- Transactions can be aborted to improve
interrupt latency
• Autonomous Multiply/Divide Unit (MDU):
- Maximum issue rate of one 32x16 multiply
per clock
- Maximum issue rate of one 32x32 multiply
every other clock
- Early-in iterative divide. Minimum 11 and
maximum 33 clock latency (dividend (rs) sign
extension-dependent)
• Power Control:
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT instruction)
- Extensive use of local gated clocks
• EJTAG Debug and Instruction Trace:
- Support for single stepping
- Virtual instruction and data address/value
-Breakpoints
FIGURE 3-1: MIPS32
®
M4K
®
PROCESSOR CORE BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 2. “CPU”
(DS60001113) in the “PIC32 Family
Reference Manual”, which is available
from the Microchip web
site
(
www.microchip.com/PIC32). Resources
for the MIPS32
®
M4K
®
Processor Core
are available at
http://www.imgtec.com.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
CPU
MDU
Execution Core
(RF/ALU/Shift)
FMT
TAP
EJTAG
Bus Interface
Power
Management
System
Co-processor
Off-chip Debug Interface
Bus Matrix
Dual Bus Interface