Datasheet
PIC32MX330/350/370/430/450/470
DS60001185C-page 286 2012-2013 Microchip Technology Inc.
TABLE 30-18: PLL CLOCK TIMING SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A +85°C for Industrial
-40°C T
A +105°C for V-temp
Param.
No.
Symbol Characteristics
(1)
Min. Typical Max. Units Conditions
OS50 F
PLLI PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
3.92 — 5 MHz ECPLL, HSPLL, XTPLL,
FRCPLL modes
OS51 F
SYS On-Chip VCO System
Frequency
60 — 120 MHz —
OS52 T
LOCK PLL Start-up Time (Lock Time) — — 2 ms —
OS53 D
CLK CLKO Stability
(2)
(Period Jitter or Cumulative)
-0.25 — +0.25 % Measured over 100 ms
period
Note 1: These parameters are characterized, but not tested in manufacturing.
2: This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for
individual time-bases on communication clocks, use the following formula:
For example, if SYSCLK = 40 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows:
EffectiveJitter
D
CLK
SYSCLK
CommunicationClock
----------------------------------------------------------
--------------------------------------------------------------
=
EffectiveJitter
D
CLK
40
20
------
--------------
D
CLK
1.41
--------------
==
TABLE 30-19: INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Param.
No.
Characteristics Min. Typical Max. Units Conditions
Internal FRC Accuracy @ 8.00 MHz
(1)
F20b FRC -0.9 — +0.9 % —
Note 1: Frequency calibrated at 25°C and 3.3V. The TUN bits can be used to compensate for temperature drift.
TABLE 30-20: INTERNAL LPRC ACCURACY
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Param.
No.
Characteristics Min. Typical Max. Units Conditions
LPRC @ 31.25 kHz
(1)
F21 LPRC -15 — +15 % —
Note 1: Change of LPRC frequency as VDD changes.