Datasheet

PIC32MX330/350/370/430/450/470
DS60001185C-page 28  2012-2013 Microchip Technology Inc.
FIGURE 2-1: RECOMMENDED
MINIMUM CONNECTION
2.2.1 BULK CAPACITORS
The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 µF
to 47
µF. This capacitor should be located as close to
the device as possible.
2.3 Capacitor on Internal Voltage
Regulator (V
CAP)
2.3.1 INTERNAL REGULATOR MODE
A low-ESR (3 ohm) capacitor is required on the VCAP
pin, which is used to stabilize the internal voltage regu-
lator output. The VCAP pin must not be connected to
VDD, and must have a CEFC capacitor, with at least a
6V rating, connected to ground. The type can be
ceramic or tantalum. Refer to
Section 30.0 “Electrical
Characteristics” for additional information on CEFC
specifications.
2.4 Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions:
• Device Reset
• Device programming and debugging
Pulling The MCLR pin low generates a device Reset.
Figure 2-2 illustrates a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the
MCLR pin. Consequently, specific voltage
levels (V
IH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.
For example, as illustrated in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components illustrated in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2: EXAMPLE OF MCLR PIN
CONNECTIONS
PIC32
VDD
VSS
VDD
VSS
VSS
VDD
AVDD AVSS VDD VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
C
R
V
DD
MCLR
0.1 µF
Ceramic
L1
(2)
R1
Note 1: If the USB module is not used, this pin must be
connected to V
DD.
2: As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between V
DD and
AV
DD to improve ADC noise rejection. The inductor
impedance should be less than 3 and the inductor
capacity greater than 10 mA.

Where:
f
F
CNV
2
--------------
=
f
1
2 LC
-----------------------
=
L
1
2fC
----------------------


2
=
(i.e., ADC conversion rate/2)
Connect
(2)
VUSB3V3
(1)
VCAP
Tantalum or
ceramic 10 µF
ESR  3
(3)
3: Aluminum or electrolytic capacitors should not be
used. ESR  3 from -40ºC to 125ºC @ SYSCLK
frequency (i.e., MIPS).
Note 1: 470 R1  1 will limit any current flowing into
MCLR
from the external capacitor C, in the event of
MCLR
pin breakdown, due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS). Ensure that the
MCLR
pin VIH and VIL specifications are met without
interfering with the Debug/Programmer tools.
2: The capacitor can be sized to prevent unintentional
Resets from brief glitches or to extend the device
Reset period during POR.
3: No pull-ups or bypass capacitors are allowed on
active debug/program PGECx/PGEDx pins.
R1
(1)
10k
V
DD
MCLR
PIC32
1 k
0.1 µF
(2)
PGECx
(3)
PGEDx
(3)
ICSP™
1
5
4
2
3
6
V
DD
VSS
NC
R
C