Datasheet

PIC32MX330/350/370/430/450/470
DS60001185C-page 186  2012-2013 Microchip Technology Inc.
bit 3 T32: 32-Bit Timer Mode Select bit
(2)
1 = Odd numbered and even numbered timers form a 32-bit timer
0 = Odd numbered and even numbered timers form a separate 16-bit timer
bit 2 Unimplemented: Read as ‘0’
bit 1 TCS: Timer Clock Source Select bit
(3)
1 = External clock from TxCK pin
0 = Internal peripheral clock
bit 0 Unimplemented: Read as ‘0’
REGISTER 14-1: TXCON: TYPE B TIMER CONTROL REGISTER (CONTINUED)
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit is available only on even numbered timers (Timer2 and Timer4).
3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer3 and Timer5). All
timer functions are set through the even numbered timers.
4: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.