PIC32MX330/350/370/430/450/470 32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM) with Audio/Graphics/Touch (HMI), USB, and Advanced Analog Operating Conditions Timers/Output Compare/Input Capture • 2.3V to 3.
PIC32MX330/350/370/430/450/470 TABLE 1: PIC32MX330/350/370/430/450/470 CONTROLLER FAMILY FEATURES Program Memory (KB)(1) Data Memory (KB) Remappable Pins Timers/Capture/Compare(2) UART SPI/I2S External Interrupts(3) 10-bit 1 Msps ADC (Channels) Analog Comparators USB On-The-Go (OTG) CTMU I2C™ PMP RTCC DMA Channels (Programmable/Dedicated) I/O Pins JTAG Trace 64+12 16 37 5/5/5 4 2/2 5 28 2 N Y 2 Y Y 4/0 53 Y N 64+12 16 54 5/5/5 5 2/2 5 28 2 N Y 2 Y Y 4/0 85
PIC32MX330/350/370/430/450/470 Pin Diagrams 64-Pin QFN(1,2,3,4) AN25/RPD2/RD2 AN24/RPD1/RD1 RPD5/PMRD/RD5 RPD4/PMWR/RD4 AN26/RPD3/RD3 VDD VCAP RD7 RD6 TRD2/AN20/PMD2/RE2 TRD1/PMD1/RE1 TRD0/PMD0/RE0 TRCLK/RPF1/RF1 RPF0/RF0 TRD3/RPE3/CTPLS/PMD3/RE3 AN21/PMD4/RE4 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AN22/RPE5/PMD5/RE5 AN23/PMD6/RE6 AN27/PMD7/RE7 AN16/C1IND/RPG6/SCK2/PMA5/RG6 AN17/C1INC/RPG7/PMA4/RG7 AN18/C2IND/RPG8/PMA3/RG8 MCLR AN19/C2INC/RPG9/PMA2/RG9 VSS VDD A
PIC32MX330/350/370/430/450/470 Pin Diagrams (Continued) 64-Pin QFN(1,2,3,4) RPD5/PMRD/RD5 RPD4/PMWR/RD4 AN26/RPD3/RD3 AN25/RPD2/SCK1/RD2 AN24/RPD1/RD1 VCAP RD7 RD6 TRCLK/RPF1/RF1 RPF0/RF0 VDD TRD3/RPE3/CTPLS/PMD3/RE3 TRD2/AN20/PMD2/RE2 TRD1/PMD1/RE1 TRD0/PMD0/RE0 AN21/PMD4/RE4 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AN22/RPE5/PMD5/RE5 AN23/PMD6/RE6 AN27/PMD7/RE7 AN16/C1IND/RPG6/SCK2/PMA5/RG6 AN17/C1INC/RPG7/PMA4/RG7 AN18/C2IND/RPG8/PMA3/RG8 MCLR AN19/C2INC/RPG9/PM
PIC32MX330/350/370/430/450/470 Pin Diagrams (Continued) 64-Pin TQFP(1,2,3) AN24/RPD1/RD1 RPD4/PMWR/RD4 AN26/RPD3/RD3 AN25/RPD2/RD2 RD6 RPD5/PMRD/RD5 VCAP RD7 VDD TRD0/PMD0/RE0 TRCLK/RPF1/RF1 RPF0/RF0 TRD2/AN20/PMD2/RE2 TRD1/PMD1/RE1 TRD3/RPE3/CTPLS/PMD3/RE3 AN21/PMD4/RE4 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AN22/RPE5/PMD5/RE5 AN23/PMD6/RE6 AN27/PMD7/RE7 AN16/C1IND/RPG6/SCK2/PMA5/RG6 AN17/C1INC/RPG7/PMA4/RG7 AN18/C2IND/RPG8/PMA3/RG8 MCLR AN19/C2INC/RPG9/PMA2
PIC32MX330/350/370/430/450/470 Pin Diagrams (Continued) 64-Pin TQFP(1,2,3) AN25/RPD2/SCK1/RD2 AN24/RPD1/RD1 RD6 RPD5/PMRD/RD5 RPD4/PMWR/RD4 AN26/RPD3/RD3 RD7 VDD VCAP TRD3/RPE3/CTPLS/PMD3/RE3 TRD2/AN20/PMD2/RE2 TRD1/PMD1/RE1 TRD0/PMD0/RE0 TRCLK/RPF1/RF1 RPF0/RF0 AN21/PMD4/RE4 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AN22/RPE5/PMD5/RE5 AN23/PMD6/RE6 AN27/PMD7/RE7 AN16/C1IND/RPG6/SCK2/PMA5/RG6 AN17/C1INC/RPG7/PMA4/RG7 AN18/C2IND/RPG8/PMA3/RG8 MCLR AN19/C2INC/RPG9/PM
PIC32MX330/350/370/430/450/470 Pin Diagrams (Continued) 100-Pin TQFP(1,2,3) RG15 VDD AN22/RPE5/PMD5/RE5 AN23/PMD6/RE6 AN27/PMD7/RE7 RPC1/RC1 RPC2/RC2 RPC3/RC3 RPC4/CTED7/RC4 AN16/C1IND/RPG6/SCK2/PMA5/RG6 AN17/C1INC/RPG7/PMA4/RG7 AN18/C2IND/RPG8/PMA3/RG8 MCLR AN19/C2INC/RPG9/PMA2/RG9 VSS VDD TMS/CTED1/RA0 RPE8/RE8 RPE9/RE9 AN5/C1INA/RPB5/RB5 AN4/C1INB/RB4 PGED3/AN3/C2INA/RPB3/RB3 PGEC3/AN2/C2INB/RPB2/CTED13/RB2 PGEC1/AN1/RPB1/CTED12/RB1 VDD VCAP PMD15/RD7 PMD14/RD6 RPD5/PMRD/RD5 RPD4/PMWR/RD4 PMD13/RD13 RP
PIC32MX330/350/370/430/450/470 Pin Diagrams (Continued) 100-Pin TQFP(1,2,3) RG15 VDD AN22/RPE5/PMD5/RE5 AN23/PMD6/RE6 AN27/PMD7/RE7 RPC1/RC1 RPC2/RC2 RPC3/RC3 RPC4/CTED7/RC4 AN16/C1IND/RPG6/SCK2/PMA5/RG6 AN17/C1INC/RPG7/PMA4/RG7 AN18/C2IND/RPG8/PMA3/RG8 MCLR AN19/C2INC/RPG9/PMA2/RG9 VSS VDD TMS/CTED1/RA0 RPE8/RE8 RPE9/RE9 AN5/C1INA/RPB5/VBUSON/RB5 AN4/C1INB/RB4 PGED3/AN3/C2INA/RPB3/RB3 PGEC3/AN2/C2INB/RPB2/CTED13/RB2 PGEC1/AN1/RPB1/CTED12/RB1 VDD VCAP PMD15/RD7 PMD14/RD6 RPD5/PMRD/RD5 RPD4/PMWR/RD4 PMD13
PIC32MX330/350/370/430/450/470 Pin Diagrams (Continued) 124-Pin VTLA(1,2,3) A68 A67 A1 = Pins are up to 5V tolerant A66 A65 A64 A63 A62 A61 A60 A59 A58 A57 A56 A55 A54 A53 A52 A51 B56 B55 B54 B53 B52 B51 B50 B49 B48 B47 B46 B45 B44 B43 B42 A50 A2 B1 A49 A3 B2 B41 A48 A4 B3 B40 A47 A5 B4 B39 A46 A6 B5 B38 A45 A7 B6 B37 A44 B36 A43 B35 A42 PIC32MX330F064L PIC32MX350F128L PIC32MX350F256L PIC32MX370F512L A8 B7 A9 B8 A10 B9 B34 A41 A11 B10
PIC32MX330/350/370/430/450/470 PIN NAMES: PIC32MX3XXL DEVICES(1,2,3,4) TABLE 2: Package Bump # Full Pin Name Package Bump # Full Pin Name A1 No Connect A52 AN24/RPD1/RD1 A2 RG15 A53 AN26/RPD3/RD3 A3 VSS A54 PMD13/RD13 A4 AN23/PMD6/RE6 A55 RPD5/PMRD/RD5 A5 RPC1/RC1 A56 PMD15/RD7 A6 RPC3/RC3 A57 No Connect A7 AN16/C1IND/RPG6/SCK2/PMA5/RG6 A58 No Connect A8 AN18/C2IND/RPG8/PMA3/RG8 A59 VDD RPF1/PMD10/RF1 A9 AN19/C2INC/RPG9/PMA2/RG9 A60 A10 VDD A61 RPG0/PMD8/RG0 A11
PIC32MX330/350/370/430/450/470 PIN NAMES: PIC32MX3XXL DEVICES(1,2,3,4) (CONTINUED) TABLE 2: Package Bump # Full Pin Name Package Bump # Full Pin Name B35 No Connect B46 No Connect B36 RPA14/RA14 B47 No Connect B37 RPD8/RTCC/RD8 B48 VCAP B38 RPD10/PMCS2/RD10 B49 RPF0/PMD11/RF0 B39 RPD0/RD0 B50 RPG1/PMD9/RG1 B40 SOSCO/RPC14/T1CK/RC14 B51 TRCLK/RA6 B41 VSS B52 PMD0/RE0 B42 AN25/RPD2/RD2 B53 VDD B43 RPD12/PMD12/RD12 B54 TRD2/RG14 B44 RPD4/PMWR/RD4 B55 TRD0/RG13 B45
PIC32MX330/350/370/430/450/470 Pin Diagrams (Continued) 124-Pin VTLA(1,2,3) A68 A67 A1 = Pins are up to 5V tolerant A66 A65 A64 A63 A62 A61 A60 A59 A58 A57 A56 A55 A54 A53 A52 A51 B56 B55 B54 B53 B52 B51 B50 B49 B48 B47 B46 B45 B44 B43 B42 A50 A2 B1 A49 A3 B2 B41 A48 A4 B3 B40 A47 A5 B4 B39 A46 A6 B5 B38 A45 A7 B6 B37 A44 A8 B7 B36 A43 A9 B8 B35 A42 A10 B9 B34 A41 A11 B10 B33 A40 A12 B11 B32 A39 A13 B12 B31 A38 A14 B13 B30
PIC32MX330/350/370/430/450/470 PIN NAMES: PIC32MX4XXL DEVICES(1,2,3,4) TABLE 3: Package Bump # Full Pin Name Package Bump # Full Pin Name A1 No Connect A52 A2 RG15 A53 AN24/RPD1/RD1 AN26/RPD3/RD3 A3 VSS A54 PMD13/RD13 A4 AN23/PMD6/RE6 A55 RPD5/PMRD/RD5 A5 RPC1/RC1 A56 PMD15/RD7 A6 RPC3/RC3 A57 No Connect No Connect A7 AN16/C1IND/RPG6/SCK2/PMA5/RG6 A58 A8 AN18/C2IND/RPG8/PMA3/RG8 A59 VDD A9 AN19/C2INC/RPG9/PMA2/RG9 A60 RPF1/PMD10/RF1 A10 VDD A61 RPG0/PMD8/RG0 A11 R
PIC32MX330/350/370/430/450/470 PIN NAMES: PIC32MX4XXL DEVICES(1,2,3,4) (CONTINUED) TABLE 3: Package Bump # Full Pin Name Package Bump # Full Pin Name B35 No Connect B46 No Connect B36 SCL1/RPA14/RA14 B47 No Connect B37 RPD8/RTCC/RD8 B48 VCAP B38 RPD10/SCK1/PMCS2/RD10 B49 RPF0/PMD11/RF0 B39 RPD0/INT0/RD0 B50 RPG1/PMD9/RG1 B40 SOSCO/RPC14/T1CK/RC14 B51 TRCLK/RA6 B41 VSS B52 PMD0/RE0 B42 AN25/RPD2/RD2 B53 VDD B43 RPD12/PMD12/RD12 B54 TRD2/RG14 B44 RPD4/PMWR/RD4 B55 T
PIC32MX330/350/370/430/450/470 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 17 2.0 Guidelines for Getting Started with 32-bit MCUs........................................................................................................................ 27 3.0 CPU.........................................................................................
PIC32MX330/350/370/430/450/470 Referenced Sources This device data sheet is based on the following individual sections of the “PIC32 Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note: • • • • • • • • • • • • • • • • • • • • • • • • • • • To access the documents listed below, browse to the documentation section of the Microchip web site (www.microchip.com). Section 1.
PIC32MX330/350/370/430/450/470 1.0 DEVICE OVERVIEW This document contains device-specific information for PIC32MX330/350/370/430/450/470 devices. Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX330/350/370/430/450/470 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type B14 I Analog 24 A15 I Analog 23 B13 I Analog 13 22 A13 I Analog AN4 12 21 B11 I Analog AN5 11 20 A12 I Analog AN6 17 26 A20 I Analog AN7 18 27 B16 I Analog AN8 21 32 A23 I Analog AN9 22 33 B19 I Analog AN10 23 34 A24 I Analog AN11 24 35 B20 I Analog AN12 27 41 B23 I Analog AN13 28 42 A28 I Analog AN14 29 43 B24 I Analog AN15 3
PIC32MX330/350/370/430/450/470 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type PPS I ST PPS I ST PPS PPS I ST PPS PPS PPS I ST IC5 PPS PPS PPS I ST OC1 PPS PPS PPS O ST Output Compare Output 1 OC2 PPS PPS PPS O ST Output Compare Output 2 OC3 PPS PPS PPS O ST Output Compare Output 3 OC4 PPS PPS PPS O ST Output Compare Output 4 OC5 PPS PPS PPS O ST Output Compare Output 5 OCFA PPS PPS PPS I ST Output Compare Fault
PIC32MX330/350/370/430/450/470 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type B14 I/O ST A15 I/O ST 23 B13 I/O ST 13 22 A13 I/O ST RB4 12 21 B11 I/O ST RB5 11 20 A12 I/O ST RB6 17 26 A20 I/O ST RB7 18 27 B16 I/O ST RB8 21 32 A23 I/O ST RB9 22 33 B19 I/O ST RB10 23 34 A24 I/O ST RB11 24 35 B20 I/O ST RB12 27 41 B23 I/O ST RB13 28 42 A28 I/O ST RB14 29 43 B24 I/O ST RB15 30 44 A29 I/O ST R
PIC32MX330/350/370/430/450/470 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type B52 I/O ST A64 I/O ST 98 A66 I/O ST 63 99 B56 I/O ST RE4 64 100 A67 I/O ST RE5 1 3 B2 I/O ST RE6 2 4 A4 I/O ST RE7 3 5 B3 I/O ST RE8 — 18 A11 I/O ST 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA RE0 60 93 RE1 61 94 RE2 62 RE3 Pin Name RE9 — 19 B10 I/O ST RF0 58 87 B49 I/O ST RF1 59 88 A60 I/O ST RF2 34(1) 52 A36 I/O ST
PIC32MX330/350/370/430/450/470 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name U1CTS Pin Type Buffer Type PPS I ST UART1 Clear to Send UART1 Ready to Send 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA PPS PPS Description U1RTS PPS PPS PPS O — U1RX PPS PPS PPS I ST UART1 Receive U1TX PPS PPS PPS O — UART1 Transmit U2CTS PPS PPS PPS I ST UART2 Clear to Send UART2 Ready to Send U2RTS PPS PPS PPS O — U2RX PPS PPS PPS I ST UART2 Receive U2TX
PIC32MX330/350/370/430/450/470 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type A21 I Analog B17 I Analog Comparator Voltage Reference (High) 34 A24 I Analog Comparator Voltage Reference (Output) 11 20 A12 I Analog C1INB 12 21 B11 I Analog C1INC 5 11 B6 I Analog C1IND 4 10 A7 I Analog C2INA 13 22 A13 I Analog C2INB 14 23 B13 I Analog C2INC 8 14 A9 I Analog 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA CVREF- 15 28 CVREF
PIC32MX330/350/370/430/450/470 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA Pin Type Buffer Type PMD3 63 99 B56 I/O TTL/ST PMD4 64 100 A67 I/O TTL/ST PMD5 1 3 B2 I/O TTL/ST PMD6 2 4 A4 I/O TTL/ST Description PMD7 3 5 B3 I/O TTL/ST PMD8 — 90 A61 I/O TTL/ST PMD9 — 89 B50 I/O TTL/ST PMD10 — 88 A60 I/O TTL/ST PMD11 — 87 B49 I/O TTL/ST PMD12 — 79 B43 I/O TTL/ST PMD13 — 80 A54
PIC32MX330/350/370/430/450/470 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type B19 I ST CTMU External Edge Input 4 B24 I ST CTMU External Edge Input 5 44 A29 I ST CTMU External Edge Input 6 — 9 B5 I ST CTMU External Edge Input 7 CTED8 — 92 A62 I ST CTMU External Edge Input 8 CTED9 — 60 A40 I ST CTMU External Edge Input 9 CTED10 21 32 A23 I ST CTMU External Edge Input 10 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA CTED4 22 33 CTED
PIC32MX330/350/370/430/450/470 NOTES: DS60001185C-page 26 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MCUS Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX330/350/370/430/450/470 RECOMMENDED MINIMUM CONNECTION Tantalum or ceramic 10 µF ESR 3(3) R1 MCLR C VSS VCAP R 0.1 µF Ceramic VDD VDD VUSB3V3(1) PIC32 VDD VSS Connect(2) 0.1 µF Ceramic 0.1 µF Ceramic VSS VDD AVSS 0.1 µF Ceramic AVDD VDD VSS 0.1 µF Ceramic L1(2) Note 1: If the USB module is not used, this pin must be connected to VDD.
PIC32MX330/350/370/430/450/470 2.5 ICSP Pins 2.7 Trace The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.
PIC32MX330/350/370/430/450/470 2.10 SOSC Design Recommendation Figure 2-4 shows the recommended Sosc circuit design. All components should be as close as possible to the SOSCI and SOSCO pins of the PIC32 device, ( 8 mm). Capacitors should be ceramic-type. FIGURE 2-4: RECOMMENDED OSCILLATOR CIRCUIT PLACEMENT 2.2 K SOSCO PIC32 SOSCI 33 pF Crystal(1) 33 pF Note 1: P/N: Epson MC-306 32.7680K-A0:ROHS. DS60001185C-page 30 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 2.11 Typical Application Connection Examples Examples of typical application connections are shown in Figure 2-5, Figure 2-6, and Figure 2-7.
PIC32MX330/350/370/430/450/470 FIGURE 2-7: LOW-COST CONTROLLERLESS (LCC) GRAPHICS APPLICATION WITH PROJECTED CAPACITIVE TOUCH PIC32MX430F064L CTMU ADC ANx Microchip mTouch™ GFX Libraries DMA LCD Display Projected Capacitive Touch Overlay PMP SRAM DS60001185C-page 32 External Frame Buffer 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 3.0 CPU Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS60001113) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). Resources for the MIPS32® M4K® Processor Core are available at http://www.imgtec.com.
PIC32MX330/350/370/430/450/470 3.2 Architecture Overview 3.2.2 The MIPS32® M4K® processor core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core: • • • • • • • • Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal Bus interfaces Power Management MIPS16e® Support Enhanced JTAG (EJTAG) Controller 3.2.
PIC32MX330/350/370/430/450/470 The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be transferred to the General Purpose Register file. In addition to the HI/LO targeted operations, the MIPS32® architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair.
PIC32MX330/350/370/430/450/470 Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. Table 3-3 lists the exception types in order of priority. TABLE 3-3: MIPS32® M4K® PROCESSOR CORE EXCEPTION TYPES Exception Description Reset Assertion MCLR or a Power-on Reset (POR). DSS DINT NMI EJTAG debug single step. EJTAG debug interrupt.
PIC32MX330/350/370/430/450/470 4.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source.For detailed information, refer to Section 3. “Memory Organization” (DS60001115) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX330/350/370/430/450/470 FIGURE 4-1: MEMORY MAP FOR DEVICES WITH 64 KB OF PROGRAM MEMORY Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD010000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD00FFFF Program Flash(2) 0xBD000000 0xA0004000 Reserved 0xA0003FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x1FC03000 Device Configurat
PIC32MX330/350/370/430/450/470 FIGURE 4-2: MEMORY MAP FOR DEVICES WITH 128 KB OF PROGRAM MEMORY Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD020000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD01FFFF Program Flash(2) 0xBD000000 0xA0008000 Reserved 0xA0007FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x1FC03000 Device Configura
PIC32MX330/350/370/430/450/470 FIGURE 4-3: MEMORY MAP FOR DEVICES WITH 256 KB OF PROGRAM MEMORY Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD040000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD03FFFF Program Flash(2) 0xBD000000 0xA0010000 Reserved 0xA000FFFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x1FC03000 Device Configura
PIC32MX330/350/370/430/450/470 FIGURE 4-4: MEMORY MAP FOR DEVICES WITH 512 KB OF PROGRAM MEMORY Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD080000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0020000 Reserved 0xA001FFFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x1FC03000 Device Configura
Special Function Register Maps Table 4-1 through Table 4-39 contain the peripheral address maps for the PIC32MX330/350/370/430/450/470 devices.
Virtual Address (BF88_#) Register Name 1000 INTCON 1010 INTSTAT 1020 IPTMR INTERRUPT REGISTER MAP 1030 IFS0 IFS1 1050 IFS2 1060 IEC0 1070 IEC1 1080 IEC2 1090 IPC0 10A0 IPC1 10B0 IPC2 10C0 IPC3 DS60001185C-page 43 10D0 IPC4 10E0 IPC5 30/14 29/13 28/12 27/11 26/10 31:16 — — 15:0 — — — — — — — MVEC — 31:16 — 15:0 — — — — — — — — — 25/9 24/8 23/7 22/6 21/5 — — — — — — — — — — INT4EP INT3EP — — — — — — TPC<2:0> — — — SRIPL<2:
Virtual Address (BF88_#) Register Name 10F0 IPC6 INTERRUPT REGISTER MAP (CONTINUED) 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 31/15 30/14 29/13 28/12 27/11 31:16 — — — CMP1IP<2:0> 15:0 — — — RTCCIP<2:0> 31:16 — — — 15:0 — — 31:16 — 15:0 23/7 22/6 21/5 CMP1IS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000 RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000 U1IP<2:0> U1IS<1:0> — — — SPI1IP<2:0> SPI1IS<1:0> 0000 — USBIP<2:0>(2) USBIS<1:0>(2) — —
Virtual Address (BF80_#) 0600 T1CON 0610 TMR1 0620 PR1 0800 T2CON TMR2 0820 PR2 0A00 T3CON 0A10 TMR3 0A20 PR3 0C00 T4CON 0C10 TMR4 0C20 PR4 0E00 T5CON 0E10 TMR5 0E20 DS60001185C-page 45 Legend: Note 1: PR5 30/14 29/13 31:16 — — — 15:0 ON 31:16 — — — SIDL — 15:0 31:16 — — — 15:0 31:16 — — 15:0 ON 31:16 — 31:16 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 — — — — TWDIS — TWIP — — — — — — — — — — — — — TGATE — — — TCKPS<1:0> — — — — —
Virtual Address (BF80_#) IC1BUF 31/15 30/14 31:16 — 15:0 ON 31:16 15:0 2210 31:16 15:0 2400 IC3CON(1) 31:16 15:0 2410 31:16 15:0 IC3BUF 2600 IC4CON(1) 31:16 15:0 2610 31:16 15:0 IC4BUF 2800 IC5CON(1) 31:16 15:0 2810 31:16 15:0 IC5BUF Legend: Note 1: 28/12 27/11 26/10 25/9 — — — — — — — SIDL — — — FEDGE 31:16 15:0 2200 IC2CON(1) IC2BUF 29/13 24/8 23/7 22/6 21/5 — — — — C32 ICTMR ICI<1:0> 20/4 19/3 18/2 — — — ICOV ICBNE 17/1 16/0 — — ICM<2:0
Virtual Address (BF80_#) 3000 OC1CON 3010 3020 OC1R OC1RS 3200 OC2CON OC2R OC2RS 3400 OC3CON 3410 OC3R 3420 OC3RS 3600 OC4CON 3610 3620 OC4R 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 — 15:0 ON — — — — — — — — — — — SIDL — — — — — — — OC32 31:16 3810 OC5R 3820 OC5RS DS60001185C-page 47 Legend: Note 1: 20/4 19/3 18/2 — — — OCFLT OCTSEL 31:16 — — OCM<2:0> OC1RS<31:0> — — — — — — — — — — — — 15:0 ON — SIDL — — — — —
Virtual Address (BF80_#) 5010 I2C1STAT 5020 I2C1ADD 5030 I2C1MSK 5040 I2C1BRG I2C1TRN 5060 I2C1RCV 5100 I2C2CON 5110 I2C2STAT 5120 I2C2ADD 5130 I2C2MSK 5140 I2C2BRG 2012-2013 Microchip Technology Inc.
U1STA(1) 6020 U1TXREG 6040 U1BRG(1) 6200 U2MODE(1) 6210 U2STA(1) 6220 U2TXREG 6230 U2RXREG 6240 U2BRG(1) 6400 U3MODE(1) 6410 U3STA(1) 6420 U3TXREG DS60001185C-page 49 6430 U3RXREG 6440 U3BRG(1) 31/15 30/14 31:16 — — — 15:0 ON — SIDL — — 31:16 15:0 UTXISEL<1:0> 29/13 28/12 27/11 26/10 25/9 24/8 — — — — — IREN RTSMD — UEN<1:0> — — — — — ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT 31:16 — — — — — — — — 15:0 — — — — — — — TX8 31:16 — —
6620 U4TXREG 6630 U4RXREG 6640 U4BRG(1) 6800 U5MODE(1) 6810 U5STA(1) 6820 U5TXREG 6830 U5RXREG 6840 U5BRG(1) Bit Range Register Name U4STA(1) 31:16 15:0 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 — — — — — — — — ON — SIDL IREN RTSMD — — — UTXISEL<1:0> UEN<1:0> — — — — — ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT 31:16 — — — — — — — — 15:0 — — — — — — — TX8 31:16 — — — — — — — — 15:0 — — — — — — — RX8 31:16 —
SPI2 AND SPI2 REGISTER MAP 5800 SPI1CON 5810 SPI1STAT 5820 SPI1BUF 31/15 31:16 FRMEN 15:0 ON 31:16 15:0 30/14 29/13 FRMSYNC FRMPOL 28/12 27/11 MSSEN FRMSYPW 26/10 25/9 24/8 DISSDO — SIDL — MODE32 MODE16 SMP RXBUFELM<4:0> — — — FRMERR SPIBUSY — — 31:16 22/6 21/5 20/4 MCLKSEL — — — CKE SSEN — CKP — MSTEN — DISSDI SPITUR SRMT SPIROV SPIRBE — FRMCNT<2:0> — — 23/7 19/3 18/2 17/1 — — SPIFE 16/0 ENHBUF 0000 STXISEL<1:0> SRXISEL<1:0> TXBUFELM<4:0> SPITBE —
Register Name 9000 AD1CON1(1) 9010 AD1CON2(1) 9020 AD1CON3(1) 9040 AD1CHS(1) (1) 9050 AD1CSSL 9070 ADC1BUF0 9080 ADC1BUF1 9090 ADC1BUF2 90A0 ADC1BUF3 90B0 ADC1BUF4 90C0 ADC1BUF5 2012-2013 Microchip Technology Inc.
ADC REGISTER MAP (CONTINUED) Register Name 9120 ADC1BUFB 9130 ADC1BUFC 9140 ADC1BUFD 9150 ADC1BUFE 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 ADC Result Word B (ADC1BUFB<31:0>) ADC Result Word C (ADC1BUFC<31:0>) ADC Result Word D (ADC1BUFD<31:0>) ADC Result Word E (ADC1BUFE<31:0>) ADC Result Word F (ADC1BUFF<31:0>) 21/5 20/4 19/3 18/2 17/1 16/0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Legend: x = unknown value on Reset; —
3000 DMACON 3010 DMASTAT 3020 DMAADDR 31/15 30/14 29/13 31:16 — — — 15:0 ON 31:16 — — — — — 15:0 — — — All Resets Bit Range Bits Register Name(1) Virtual Address (BF88_#) DMA GLOBAL REGISTER MAP 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — 0000 — — — — — — — — — — — — — — — — — — — — — — 0000 0000 — — — — — — — RDWR SUSPEND DMABUSY — — — — 31:16 DMACH<2:0> 0000 0000 DMAADDR<31:0> 15:0
Virtual Address (BF88_#) 3060 DCH0CON 3070 DCH0ECON 3080 DCH0INT 3090 DCH0SSA 30B0 DCH0SSIZ 30C0 DCH0DSIZ 30D0 DCH0SPTR 30E0 DCH0DPTR 30F0 DCH0CSIZ 3100 DCH0CPTR 3110 DCH0DAT 3120 DCH1CON 3130 DCH1ECON DCH1INT DS60001185C-page 55 3150 DCH1SSA 3160 DCH1DSA Legend: Note 1: 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — — — — — — — — — — — — — — — CHCHNS — CHEN CHAED CHCHN CHAEN — CHAIRQ<7:0> CHEDET — — — 31:16 — — — CHSIRQ<7:0> — — — — — CFORCE CABORT CHSDIE CHSH
Virtual Address (BF88_#) 3180 DCH1DSIZ 3190 DCH1SPTR 31A0 DCH1DPTR 31B0 DCH1CSIZ 31C0 DCH1CPTR 31D0 DCH1DAT 31E0 DCH2CON 31F0 DCH2ECON DCH2INT 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — CHSSIZ<15:0> All Resets Bit Range Register Name(1) Bits 3170 DCH1SSIZ 3200 DMA CHANNEL 0 THROUGH CHANNEL 3 REGISTER MAP (CONTINUED) 0000 0000 — — — — — — — — — CHDSIZ<15:0> — — —
Virtual Address (BF88_#) DMA CHANNEL 0 THROUGH CHANNEL 3 REGISTER MAP (CONTINUED) 3280 DCH2CPTR 3290 DCH2DAT 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 32B0 DCH3ECON DCH3INT 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — 0000 — — CHPRI<1:0> 0000 0000 — — 00FF FFF8 31:16 — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — — CHCHNS — — — — CHSIRQ<7:0> — — — 31:16 — 15:0
Virtual Address (BF80_#) COMPARATOR REGISTER MAP A000 CM1CON A010 CM2CON A060 CMSTAT 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 — Note 1: 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — 0000 15:0 ON COE CPOL 31:16 — — — — — — — — — — — COUT — EVPOL<1:0> — — — — CREF — — — — — CCH<1:0> — — E1C3 0000 15:0 ON COE CPOL 31:16 — — — — — — — — — — — COUT — EVPOL<1:0> — — — — CREF — — — — — CCH<1:0> — — E1C3 0000 —
Virtual Address (BF80_#) FLASH CONTROLLER REGISTER MAP F400 NVMCON(1) NVMKEY F420 NVMADDR(1) F430 NVMDATA F440 NVMSRC ADDR Legend: Note 1: 30/14 29/13 31:16 — — — 15:0 WR WREN WRERR 31:16 15:0 31:16 15:0 31:16 15:0 31:16 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 — — — — — — — — — — — — — — — — — LVDERR LVDSTAT 18/2 17/1 16/0 — — — NVMOP<3:0> NVMKEY<31:0> NVMADDR<31:0> NVMDATA<31:0> NVMSRCADDR<31:0> 15:0 x = unknown value on Reset; — = unimp
Virtual Address (BF80_#) F010 OSCTUN F020 REFOCON F030 REFOTRIM 0000 WDTCON F600 RCON F610 RSWRST F200 CFGCON SYSKEY(3) 2012-2013 Microchip Technology Inc.
DEVCFG: DEVICE CONFIGURATION WORD SUMMARY 2FF4 DEVCFG2 2FF8 DEVCFG1 2FFC DEVCFG0 29/13 28/12 31:16 FVBUSONIO FUSBIDIO IOL1WAY PMDL1WAY 15:0 31:16 15:0 31:16 27/11 26/10 25/9 — — — 24/8 23/7 22/6 21/5 20/4 19/3 — — — — — — Virtual Address (BF80_#) Register Name DEVID 16/0 FSRSSEL<2:0> xxxx — — — — — — — — — — — — — — UPLLIDIV<2:0>(1) — FPLLMUL<2:0> — FWDTWINSZ<1:0> FWDTEN WINDIS — — — 15:0 FCKSM<1:0> FPBDIV<1:0> — — — CP OSCIOFNC — — — — xxxx UPLLEN(1) — P
6010 6020 6030 6040 TRISA PORTA LATA ODCA 6050 CNPUA 6060 CNPDA 6070 CNCONA 6080 CNENA 2012-2013 Microchip Technology Inc.
PORTB REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits Register Name(1) Virtual Address (BF88_#) 2012-2013 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name(1) 6210 TRISC 6220 PORTC 6230 LATC 6240 ODCC 6250 CNPUC 6260 CNPDC CNENC 6290 CNSTATC Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits 6270 CNCONC 6280 PORTC REGISTER MAP FOR PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L, PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, AND PIC32MX470F512L DEVICES ONLY 31:16 — — — — — — — —
Virtual Address (BF88_#) Register Name(1) 6210 TRISC 6220 PORTC 6230 LATC 6240 ODCC 6250 CNPUC 6260 CNPDC 6290 CNSTATC Legend: Note 1: 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 31:16 TRISC15 — TRISC14 — TRISC13 — TRISC12 — — — — — — — — — — — — — — — — — — — — — — — — — xxxx 0000 15:0 31:16 RC15 — RC14 — RC13 — RC12 — — — — — — — — — — — — — — —
Virtual Address (BF88_#) Register Name(1) 6300 ANSELD 6310 TRISD 5320 PORTD 6330 LATD 6340 ODCD 6350 CNPUD 6360 CNPDD CNEND 6390 CNSTATD Legend: Note 1: 19/3 18/2 17/1 16/0 All Resets Bit Range Bits 6370 CNCOND 6380 PORTD REGISTER MAP FOR PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L, PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, AND PIC32MX470F512L DEVICES ONLY — — — — 0000 — — 00E0 0000 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7
TRISD 5320 PORTD 6330 LATD 6340 ODCD 6350 CNPUD 6360 CNPDD 6370 CNCOND CNEND 6390 CNSTATD Legend: Note 1: Bit Range 18/2 17/1 16/0 — — — — 0000 — — 00E0 0000 TRISD1 — TRISD0 — xxxx 0000 RD2 — RD1 — RD0 — xxxx 0000 LATD3 — LATD2 — LATD1 — LATD0 — xxxx 0000 ODCD3 — ODCD2 — ODCD1 — ODCD0 — xxxx 0000 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 31:16 — — — — — — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — —
Virtual Address (BF88_#) Register Name(1) 6400 ANSELE 6410 TRISE 6420 PORTE 6440 LATE 6440 ODCE 6450 CNPUE 6460 CNPDE 6470 CNCONE 6480 CNENE PORTE REGISTER MAP FOR PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L, PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, PIC32MX470F512L DEVICES ONLY Legend: Note 1: 18/2 17/1 16/0 All Resets 6490 CNSTATE Bit Range Bits — — — — 0000 — — ANSELE2 — — — — — 00F4 0000 TRISE4 — TRISE3 — TRISE2 — TRISE1 — TRISE0
Virtual Address (BF88_#) Register Name(1) 6400 ANSELE 6410 TRISE 6420 PORTE 6440 LATE 6440 ODCE 6450 CNPUE 6460 CNPDE 6490 CNSTATE Legend: Note 1: 17/1 16/0 — — — — 0000 — — ANSELE2 — — — — — 00F4 0000 TRISE4 — TRISE3 — TRISE2 — TRISE1 — TRISE0 — xxxx 0000 RE5 — RE4 — RE3 — RE2 — RE1 — RE0 — xxxx 0000 LATE6 — LATE5 — LATE4 — LATE3 — LATE2 — LATE1 — LATE0 — xxxx 0000 ODCE7 — ODCE6 — ODCE5 — ODCE4 — ODCE3 — ODCE2 — ODCE1 — ODCE0 — xxxx 0000 — — CNPUE
Virtual Address (BF88_#) Register Name(1) 6510 TRISF 6520 PORTF 6530 LATF 6540 ODCF 6550 CNPUF 6560 CNPDF 6590 CNSTATF Legend: Note 1: 31/15 30/14 31:16 — — 15:0 31:16 — — — — 15:0 31:16 — — — — 15:0 31:16 — — 15:0 31:16 29/13 24/8 16/0 All Resets CNENF Bit Range Bits 6570 CNCONF 6580 PORTF REGISTER MAP FOR PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, AND PIC32MX370F512L DEVICES ONLY — — 0000 TRISF1 — TRISF0 — xxxx 0000 RF1 — RF0 — xxxx 0000 LATF2 — LATF
Virtual Address (BF88_#) Register Name(1) 6510 TRISF 6520 PORTF 6530 LATF 6540 ODCF 6550 CNPUF 6560 CNPDF 6590 CNSTATF Legend: Note 1: 30/14 31:16 — — 15:0 31:16 — — — — 15:0 31:16 — — — — 15:0 31:16 — — 15:0 31:16 29/13 28/12 27/11 26/10 25/9 — — — — TRISF13 — TRISF12 — — — — — RF13 — RF12 — — — — — LATF13 — LATF12 — — — — — ODCF13 — ODCF12 — 15:0 31:16 — — — — 15:0 31:16 — — — — 15:0 31:16 ON — — — SIDL — 15:0 31:16 — — — — 15:0 — — 16/0
Virtual Address (BF88_#) Register Name(1) 6510 TRISF 6520 PORTF 6530 LATF 6540 ODCF 6550 CNPUF 6560 CNPDF 6590 CNSTATF Legend: Note 1: 16/0 All Resets CNENF Bit Range Bits 6570 CNCONF 6580 PORTF REGISTER MAP FOR PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, AND PIC32MX370F512H DEVICES ONLY — — 0000 TRISF1 — TRISF0 — xxxx 0000 RF1 — RF0 — xxxx 0000 LATF2 — LATF1 — LATF0 — xxxx 0000 ODCF3 — ODCF2 — ODCF1 — ODCF0 — xxxx 0000 CNPUF4 — CNPUF3 — CNPUF2 — CNPUF1 — C
Virtual Address (BF88_#) Register Name(1) 6510 TRISF 6520 PORTF 6530 LATF 6540 ODCF 6550 CNPUF 6560 CNPDF 6590 CNSTATF Legend: Note 1: — — 0000 TRISF1 — TRISF0 — xxxx 0000 RF1 — RF0 — xxxx 0000 — — LATF1 — LATF0 — xxxx 0000 ODCF3 — — — ODCF1 — ODCF0 — xxxx 0000 CNPUF4 — CNPUF3 — — — CNPUF1 — CNPUF0 xxxx — 0000 CNPDF5 — CNPDF4 — CNPDF3 — — — CNPDF1 — CNPDF0 xxxx — 0000 — — — — — — — — — — — — — — 0000 0000 — — — — CNIEF5 — CNIEF4 — CNIEF3 — — — CNIEF1
TRISG 6620 PORTG 6630 LATG 6640 ODCG 6650 CNPUG 6660 CNPDG 6670 CNCONG CNENG 6690 CNSTATG Legend: Note 1: 2012-2013 Microchip Technology Inc.
TRISG 6620 PORTG 6630 LATG 6640 ODCG 6650 CNPUG 6660 CNPDG 6670 CNCONG CNENG 6690 CNSTATG Legend: Note 1: 2: Bit Range 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — 0000 — — — — — — — — — — — — 01C0 0000 TRISG6 — — — — — TRISG3 — TRISG2 — — — — — xxxx 0000 RG7 — RG6 — — — — — RG3(2) — RG2(2) — — — — — xxxx 0000 LATG8 — LATG7 — LATG6 — — — — — LATG3 — LATG2 — — — — — xxxx 0000 ODCG9 — ODCG8 — ODCG7 — ODCG6 — — — — —
FA08 INT2R FA0C INT3R FA10 INT4R FA18 T2CKR FA1C T3CKR FA20 T4CKR FA24 T5CKR FA28 IC1R FA2C IC2R FA30 IC3R FA34 IC4R FA38 IC5R FA48 OCFAR FA50 U1RXR 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 —
U2RXR FA5C U2CTSR FA60 U3RXR FA64 U3CTSR FA68 U4RXR FA6C U4CTSR FA70 U5RXR FA74 U5CTSR FA84 SDI1R FA88 SS1R FA90 SDI2R FA94 SS2R DS60001185C-page 77 FAD0 REFCLKIR 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 31:16 — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — —
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 2012-2013 Microchip Technology Inc.
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 RPC4R(1) 22/6 21/5 20/4 19/3 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 18/2 17/1 — — RPC4<3:0> — — RPC13<3:0> — — RPC14<3:0> —
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 2012-2013 Microchip Technology Inc.
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 — — — — — — — — 31:16 15:0 — — — — — — — — — — — — — — — — 31:16 FCA4 RPG9R 15:0 — — — — — — — — Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register is not available on 64-pin devices. 2: This register is only available on devices without a USB module. 3: This register is not available on 64-pin devices with a USB module.
Virtual Address (BF80_#) Register Name(1) 7000 PMCON PARALLEL MASTER PORT REGISTER MAP 7010 PMMODE 7020 PMADDR 31/15 30/14 31:16 — — — 15:0 ON — — SIDL — 31:16 — 15:0 31:16 BUSY — — 15:0 CS2 CS1 29/13 IRQM<1:0> — 28/12 27/11 — — ADRMUX<1:0> — — INCM<1:0> — — 26/10 25/9 24/8 23/7 22/6 — — — — — PMPTTL PTWREN PTRDEN — — — MODE16 — MODE<1:0> WAITB<1:0> — — PMDIN 7050 PMAEN 7060 PMSTAT Legend: Note 1: 31:16 15:0 31:16 — — — — — — — 15:0 31:16 — — 2
4010 CHEACC(1) 4020 CHETAG(1) 4030 CHEMSK(1) CHEW0 4050 CHEW1 4060 CHEW2 4070 CHEW3 4080 CHELRU 4090 CHEHIT CHEMIS 40C0 CHEPFABT Legend: Note 1: 30/14 29/13 28/12 27/11 26/10 — — — — — — — — — — — — 31:16 CHEWEN — — — — 15:0 — — — — — — — — 31:16 15:0 — 31:16 LTAGBOOT — — — — — 15:0 23/7 22/6 — — DCSZ<1:0> — — — — — — — — — — — — — — — — — — LMASK<15:5> — 31:16 31:16 31:16 31:16 31:16 15:0 31:16 — — — — — 18/2 17/1 — — — — — — CHEIDX<3:0> 16/
Virtual Address (BF80_#) Register Name(1) 0200 RTCCON RTCC REGISTER MAP 0210 RTCALRM 0220 RTCTIME 0230 RTCDATE 0240 ALRMTIME 0250 ALRMDATE — 15:0 ON 31:16 — 15:0 ALRMEN 28/12 27/11 26/10 — — — — — — — SIDL — — — — — — — CHIME PIV HR10<3:0> ALRMSYNC 25/9 24/8 — — — — SEC01<3:0> YEAR01<3:0> 15:0 DAY10<3:0> DAY01<3:0> 31:16 HR10<3:0> HR01<3:0> SEC10<3:0> — SEC01<3:0> — — — 19/3 18/2 17/1 16/0 — — — — 0000 RTCWREN RTCSYNC HALFSEC RTCOE — — — — ARPT<7:0> SEC10<3:
Virtual Address (BF88_#) Register Name(1) 5040 U1OTGIR(2) 5050 U1OTGIE 5060 U1OTGSTAT(3) 5080 U1PWRC 5200 U1IR(2) 5210 U1IE 5220 U1EIR(2) 5230 U1EIE U1STAT(3) 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — IDIF — T1MSECIF LSTATEIF — — ACTVIF — SESVDIF SESENDIF — — — — VBUSVDIF 0000 — 0000 — — — — — — — — — — — — — — — — IDIE — T1MSECIE LSTATEIE — — ACTVIE — SESVDIE SESENDIE — — — — VBUSVDIE 0
Virtual Address (BF88_#) Register Name(1) 5280 U1FRML(3) 5290 U1FRMH(3) USB REGISTER MAP (CONTINUED) 52A0 U1TOK 2012-2013 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name(1) 5390 U1EP9 53A0 U1EP10 USB REGISTER MAP (CONTINUED) 53B0 U1EP11 53C0 U1EP12 U1EP13 53E0 U1EP14 53F0 U1EP15 Legend: Note 1: 2: 3: 4: 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — — — — — — — — — — — EPCONDIS EPRXEN — — EPTXEN — EPSTALL — EPHSHK — 0000 0000 — — — — — — — — — — — — — — — — — — — — — — EPCONDIS EPRXEN — — EP
PIC32MX330/350/370/430/450/470 4.3 Control Registers Register 4-1 through Register 4-8 are used for setting the RAM and Flash memory partitions for data and code.
PIC32MX330/350/370/430/450/470 REGISTER 4-2: Bit Range 31:24 23:16 15:8 7:0 BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXDKPBA<15:8> R-0 R-0 BMXDKPBA<7:0> Leg
PIC32MX330/350/370/430/450/470 REGISTER 4-3: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 BMXDUDBA<15:8> R-0 7:0 BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER R-0 R-0 R-0 R-0 BMXDUDBA<7:0> Legend:
PIC32MX330/350/370/430/450/470 REGISTER 4-4: Bit Range 31:24 23:16 15:8 7:0 BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXDUPBA<15:8> R-0 R-0 BMXDUPBA<7:0> Legen
PIC32MX330/350/370/430/450/470 REGISTER 4-5: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R R R Bit Bit 28/20/12/4 27/19/11/3 R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R R R R R R BMXDRMSZ<31:24> R R R R R BMXDRMSZ<23:16> R R R R R BMXDRMSZ<15:8> R 7:0 BMXDRMSZ: DATA RAM SIZE REGISTER R R R R BMXDRMSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘
PIC32MX330/350/370/430/450/470 REGISTER 4-7: Bit Range 31:24 23:16 15:8 7:0 BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R R R Bit Bit 28/20/12/4 27/19/11/3 R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R R R R R R BMXPFMSZ<31:24> R R R R R R R R BMXPFMSZ<23:16> R R BMXPFMSZ<15:8> R R R R R BMXPFMSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit
PIC32MX330/350/370/430/450/470 NOTES: DS60001185C-page 94 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 5.0 FLASH PROGRAM MEMORY Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. “Flash Program Memory” (DS60001121) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX330/350/370/430/450/470 5.
PIC32MX330/350/370/430/450/470 REGISTER 5-2: Bit Range 31:24 23:16 15:8 7:0 NVMKEY: PROGRAMMING UNLOCK REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<31:24> W-0 NVMKEY<23:16> W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<15:8> W-0 NVMKEY<7:0> Legend: R = Readable bit W = Writable bit U = Unimplement
PIC32MX330/350/370/430/450/470 REGISTER 5-4: Bit Range 31:24 23:16 15:8 7:0 NVMDATA: FLASH PROGRAM DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDA
PIC32MX330/350/370/430/450/470 6.0 RESETS Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. “Resets” (DS60001118) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX330/350/370/430/450/470 6.
PIC32MX330/350/370/430/450/470 REGISTER 6-2: Bit Range 31:24 23:16 15:8 7:0 RSWRST: SOFTWARE RESET REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — Legend: HC = Cleared by hardwar
PIC32MX330/350/370/430/450/470 NOTES: DS60001185C-page 102 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 7.0 INTERRUPT CONTROLLER The PIC32MX330/350/370/430/450/470 module includes the following features: Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Interrupt Controller” (DS60001108) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.
PIC32MX330/350/370/430/450/470 TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION Interrupt Source(1) IRQ # Vector # Interrupt Bit Location Flag Enable Priority Sub-priority Persistent Interrupt Highest Natural Order Priority CT – Core Timer Interrupt 0 0 IFS0<0> IEC0<0> IPC0<4:2> IPC0<1:0> No CS0 – Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> No CS1 – Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> No INT0 – External Interrupt 3
PIC32MX330/350/370/430/450/470 TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED) Interrupt Bit Location Interrupt Source(1) IRQ # Vector # Flag Enable Priority Sub-priority Persistent Interrupt CNB – PORTB Input Change Interrupt 45 33 IFS1<13> IEC1<13> IPC8<12:10> IPC8<9:8> Yes CNC – PORTC Input Change Interrupt 46 33 IFS1<14> IEC1<14> IPC8<12:10> IPC8<9:8> Yes CND – PORTD Input Change Interrupt 47 33 IFS1<15> IEC1<15> IPC8<12:10> IPC8<9:8> Yes CNE – PORTE Input
PIC32MX330/350/370/430/450/470 7.
PIC32MX330/350/370/430/450/470 REGISTER 7-2: Bit Range 31:24 23:16 15:8 7:0 INTSTAT: INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — U-0 U-0 R/W-0 R/W-0 R/W-0 — — SRIPL<2:0>(1) R/W-0 R/W-0 R/W-0 VEC<5:0>(1)
PIC32MX330/350/370/430/450/470 REGISTER 7-4: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 IFSx: INTERRUPT FLAG STATUS REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS31 IFS30 IFS29 IFS28 IFS27 IFS26 IFS25 IFS24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS23 IFS22 IFS21 IFS20 IFS19 IFS18 IFS17 IFS16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS15 I
PIC32MX330/350/370/430/450/470 REGISTER 7-6: Bit Range IPCx: INTERRUPT PRIORITY CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — 31:24 23:16 15:8 7:0 Legend: R = Readable bit -n = Value at POR Bit Bit 28/20/12/4 27/19/11/3 W = Writable bit ‘1’ = Bit is set R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 IP3<2:0> R/W-0 R/W-0 IS3<1:0> R/W-0 IP2<2:0> R/W-0 R
PIC32MX330/350/370/430/450/470 REGISTER 7-6: bit 9-8 bit 7-5 bit 4-2 IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED) IS1<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as ‘0’ IP0<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 • • • bit 1-0 Note: 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IS0<1:0>: Interrupt
PIC32MX330/350/370/430/450/470 8.0 OSCILLATOR CONFIGURATION Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/ 430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 6. “Oscillator Configuration” (DS60001112) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX330/350/370/430/450/470 FIGURE 8-1: PIC32MX330/350/370/430/450/470 FAMILY CLOCK DIAGRAM USB PLL(5) USB Clock (48 MHz) div x UFIN div 2 PLL x24 UFRCEN UFIN 4 MHz UPLLIDIV<2:0> UPLLEN 96 MHz ROTRIM<8:0> (M) REFCLKI POSC FRC LPRC SOSC PBCLK SYSCLK FVCO System PLL 4 MHz FIN 5 MHz FIN div x PLL REFCLKO M 2 N + --------512 To SPI RODIV<14:0> (N) ROSEL<3:0> FPLLIDIV<2:0> COSC<2:0> OE PLLMULT<2:0> div y XTPLL, HSPLL, ECPLL, FRCPLL PLLODIV<2:0> Primary Oscillator (POSC) OSC
PIC32MX330/350/370/430/450/470 8.
PIC32MX330/350/370/430/450/470 REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 18-16 PLLMULT<2:0>: Phase-Locked Loop (PLL) Multiplier bits 111 = Clock is multiplied by 24 110 = Clock is multiplied by 21 101 = Clock is multiplied by 20 100 = Clock is multiplied by 19 011 = Clock is multiplied by 18 010 = Clock is multiplied by 17 001 = Clock is multiplied by 16 000 = Clock is multiplied by 15 bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits 111 = In
PIC32MX330/350/370/430/450/470 REGISTER 8-1: bit 3 bit 2 bit 1 bit 0 Note 1: Note: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected UFRCEN: USB FRC Clock Enable bit(1) 1 = Enable FRC as the clock source for the USB clock source 0 = Use the Primary Oscillator or USB PLL as the USB clock source SOSCEN: Secondary Oscillator (SOSC) Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillato
PIC32MX330/350/370/430/450/470 REGISTER 8-2: Bit Range 31:24 23:16 15:8 7:0 OSCTUN: FRC TUNING REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN<5:0>(1) Legend: y = Valu
PIC32MX330/350/370/430/450/470 REGISTER 8-3: Bit Range 31:24 23:16 15:8 7:0 REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — R/W-0 RODIV<14:8> R/W-0 R/W-0 R/W-0 R/W-0 RODIV<7:0> Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (3) (3) R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R-0, HS, HC ON — SIDL OE RSLP(2) — DIVSWEN ACTIVE U-0 U-
PIC32MX330/350/370/430/450/470 REGISTER 8-3: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER (CONTINUED) bit 3-0 ROSEL<3:0>: Reference Clock Source Select bits(1) 1111 = Reserved; do not use • • • 1001 = Reserved; do not use 1000 = REFCLKI 0111 = System PLL output 0110 = USB PLL output 0101 = SOSC 0100 = LPRC 0011 = FRC 0010 = POSC 0001 = PBCLK 0000 = SYSCLK Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result.
PIC32MX330/350/370/430/450/470 REGISTER 8-4: Bit Range 31:24 23:16 15:8 7:0 REFOTRIM: REFERENCE OSCILLATOR TRIM REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 ROTRIM<8:1> R/W-0 U-0 U-0 U-0 U-0 ROTRIM<0> — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — —
PIC32MX330/350/370/430/450/470 NOTES: DS60001185C-page 120 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 9.0 PREFETCH CACHE Prefetch cache increases performance for applications executing out of the cacheable program Flash memory regions by implementing instruction caching, constant data caching and instruction prefetching. Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4.
PIC32MX330/350/370/430/450/470 9.
PIC32MX330/350/370/430/450/470 REGISTER 9-2: Bit Range 31:24 23:16 15:8 7:0 CHEACC: CACHE ACCESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 CHEWEN — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CHEIDX<3:0> Legend
PIC32MX330/350/370/430/450/470 REGISTER 9-3: Bit Range 31:24 23:16 15:8 7:0 CHETAG: CACHE TAG REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 LTAGBOOT — — — — — — — R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-0 R/W-0 R/W-1 U-0 LVALID LLOCK LTYPE — LTAG<19:12> R/W-x LTAG<11:4> R/W-x R/W-x R/W-x R/
PIC32MX330/350/370/430/450/470 REGISTER 9-4: Bit Range 31:24 23:16 15:8 7:0 CHEMSK: CACHE TAG MASK REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LMASK<10:3> LMASK<2:0> U-0 U-0 U-0 U-0 U-0 — — — — — Legend:
PIC32MX330/350/370/430/450/470 REGISTER 9-6: Bit Range 31:24 23:16 15:8 7:0 CHEW1: CACHE WORD 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW1<31:24> R/W-x R/W-x CHEW1<23:16> R/W-x CHEW1<15:8> R/W-x CHEW1<7:0> Legend: R = Re
PIC32MX330/350/370/430/450/470 REGISTER 9-8: Bit Range 31:24 23:16 15:8 7:0 CHEW3: CACHE WORD 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW3<31:24> R/W-x R/W-x CHEW3<23:16> R/W-x CHEW3<15:8> R/W-x CHEW3<7:0> Legend: R = Re
PIC32MX330/350/370/430/450/470 REGISTER 9-10: Bit Range 31:24 23:16 15:8 7:0 CHEHIT: CACHE HIT STATISTICS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEHIT<31:24> R/W-x R/W-x CHEHIT<23:16> R/W-x CHEHIT<15:8> R/W-x CHEH
PIC32MX330/350/370/430/450/470 REGISTER 9-12: Bit Range 31:24 23:16 15:8 7:0 CHEPFABT: PREFETCH CACHE ABORT STATISTICS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEPFABT<31:24> R/W-x R/W-x CHEPFABT<23:16> R/W-x R/W-x CHEPFABT<15:8>
PIC32MX330/350/370/430/450/470 NOTES: DS60001185C-page 130 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 10.0 DIRECT MEMORY ACCESS (DMA) CONTROLLER Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. “Direct Memory Access (DMA) Controller” (DS60001117) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX330/350/370/430/450/470 10.
PIC32MX330/350/370/430/450/470 REGISTER 10-2: Bit Range 31:24 23:16 15:8 7:0 DMASTAT: DMA STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — RDWR DMACH<2:0> Legend: R = Read
PIC32MX330/350/370/430/450/470 REGISTER 10-4: Bit Range 31:24 23:16 15:8 7:0 DCRCCON: DMA CRC CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 R/W-0 R/W-0 — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 U-0 U-0 R/W-0 WBO(1) — — BITO U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BYTO<1:0> PLEN<4:0> R/W-0 R/W-0 R/W-0 U-0 U-0 CRCEN CR
PIC32MX330/350/370/430/450/470 REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED) bit 6 CRCAPP: CRC Append Mode bit(1) 1 = The DMA transfers data from the source into the CRC but NOT to the destination.
PIC32MX330/350/370/430/450/470 REGISTER 10-5: Bit Range 31:24 23:16 15:8 7:0 DCRCDATA: DMA CRC DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<23:16> R/W-0 R/W-0 DCRCDATA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRC
PIC32MX330/350/370/430/450/470 REGISTER 10-7: Bit Range 31:24 23:16 15:8 7:0 DCHxCON: DMA CHANNEL ‘x’ CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 CHBUSY — — — — — — CHCHNS(1) R/W-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R/W-0 CHAED CHCH
PIC32MX330/350/370/430/450/470 REGISTER 10-8: Bit Range 31:24 23:16 DCHxECON: DMA CHANNEL ‘x’ EVENT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 (1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CHAIRQ<7:0> 15:8 R/W-1 CHSIRQ<7:0>(1) 7:0 S-0 S-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 C
PIC32MX330/350/370/430/450/470 REGISTER 10-9: Bit Range 31:24 23:16 15:8 7:0 DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0
PIC32MX330/350/370/430/450/470 REGISTER 10-9: DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER (CONTINUED) bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit 1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2) 0 = No interrupt is pending bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag bit 1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a pattern match event occurs 0 = No interrupt is pen
PIC32MX330/350/370/430/450/470 REGISTER 10-10: DCHxSSA: DMA CHANNEL ‘x’ SOURCE START ADDRESS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 31:24 Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<31:24> 23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<23:16> 15:8 R/W-0 R/W-0 CHSSA<15:8> R/W-0 7:0 R/W-0 R/W-0 R
PIC32MX330/350/370/430/450/470 REGISTER 10-12: DCHxSSIZ: DMA CHANNEL ‘x’ SOURCE SIZE REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSIZ<15:8> 7:0 R/W-0 CHSSI
PIC32MX330/350/370/430/450/470 REGISTER 10-14: DCHxSPTR: DMA CHANNEL ‘x’ SOURCE POINTER REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHSPTR<15:8> 7:0 R-0 R-0 CHSPTR<7:0> Legend: R = Readable
PIC32MX330/350/370/430/450/470 REGISTER 10-16: DCHxCSIZ: DMA CHANNEL ‘x’ CELL-SIZE REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHCSIZ<15:8> 7:0 R/W-0 CHCSIZ<
PIC32MX330/350/370/430/450/470 REGISTER 10-18: DCHxDAT: DMA CHANNEL ‘x’ PATTERN DATA REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHPDAT<7:0>
PIC32MX330/350/370/430/450/470 NOTES: DS60001185C-page 146 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 11.0 USB ON-THE-GO (OTG) Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 27. “USB On-The-Go (OTG)” (DS60001126) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX330/350/370/430/450/470 FIGURE 11-1: PIC32MX430/450/470 USB INTERFACE DIAGRAM USBEN FRC Oscillator 8 MHz Typical USB Suspend CPU Clock Not POSC Sleep TUN<5:0>(3) Primary Oscillator (POSC) Div x OSC1 UFIN(4) PLL UPLLEN(5) UPLLIDIV(5) USB Suspend OSC2 (PB Out)(1) Div 2 UFRCEN(2) To Clock Generator for Core and Peripherals Sleep or Idle USB Module SRP Charge Bus SRP Discharge USB Voltage Comparators 48 MHz USB Clock(6) Full Speed Pull-up D+ Registers and Control Interface Host Pull-do
PIC32MX330/350/370/430/450/470 11.
PIC32MX330/350/370/430/450/470 REGISTER 11-2: Bit Range 31:24 23:16 15:8 7:0 U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 IDIE T1MSECIE LS
PIC32MX330/350/370/430/450/470 REGISTER 11-3: Bit Range 31:24 23:16 15:8 7:0 U1OTGSTAT: USB OTG STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 U-0 R-0 U-0 R-0 R-0 U-0 R-0 ID — LSTATE — SESVD SESEND — VBUS
PIC32MX330/350/370/430/450/470 REGISTER 11-4: Bit Range 31:24 23:16 15:8 7:0 U1OTGCON: USB OTG CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VBUSON OTGEN VBUSCHG
PIC32MX330/350/370/430/450/470 REGISTER 11-5: Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U1PWRC: USB POWER CONTROL REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UACTPND — — USLPGRD USBBUSY —
PIC32MX330/350/370/430/450/470 REGISTER 11-6: Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U1IR: USB INTERRUPT REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R-0 IDLEIF TRNIF
PIC32MX330/350/370/430/450/470 REGISTER 11-7: Bit Range 31:24 23:16 15:8 7:0 U1IE: USB INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IDLEIE TRNIE SOFIE
PIC32MX330/350/370/430/450/470 REGISTER 11-8: Bit Range 31:24 23:16 15:8 7:0 U1EIR: USB ERROR INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS
PIC32MX330/350/370/430/450/470 REGISTER 11-8: U1EIR: USB ERROR INTERRUPT STATUS REGISTER (CONTINUED) bit 1 CRC5EF: CRC5 Host Error Flag bit(4) 1 = Token packet rejected due to CRC5 error 0 = Token packet accepted EOFEF: EOF Error Flag bit(3,5) 1 = EOF error condition detected 0 = No EOF error condition bit 0 PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed Note 1: 2: 3: 4: 5: This type of error occurs when the module’s request for the DMA bus is not granted in time to serv
PIC32MX330/350/370/430/450/470 REGISTER 11-9: Bit Range 31:24 23:16 15:8 7:0 U1EIE: USB ERROR INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTSEE BMXEE D
PIC32MX330/350/370/430/450/470 REGISTER 11-10: U1STAT: USB STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-x R-x R-x R-x R-x R-x U-0 U-0 DIR PPBI — — ENDPT<3:0> Legend: R = Readab
PIC32MX330/350/370/430/450/470 REGISTER 11-11: U1CON: USB CONTROL REGISTER Bit Bit Bit Range 31/23/15/7 30/22/14/6 31:24 23:16 15:8 7:0 U-0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-x R-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 JSTATE SE0 PKTDIS(4) TOKBUSY(1,5)
PIC32MX330/350/370/430/450/470 REGISTER 11-11: U1CON: USB CONTROL REGISTER (CONTINUED) bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Even/Odd buffer pointers to the EVEN BD banks 0 = Even/Odd buffer pointers not being Reset bit 0 USBEN: USB Module Enable bit(4) 1 = USB module and supporting circuitry enabled 0 = USB module and supporting circuitry disabled SOFEN: SOF Enable bit(5) 1 = SOF token sent every 1 ms 0 = SOF token disabled Note 1: 2: 3: 4: 5: Software is required to check this bit
PIC32MX330/350/370/430/450/470 REGISTER 11-12: U1ADDR: USB ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPDEN DEVADDR<6:0> Legend:
PIC32MX330/350/370/430/450/470 REGISTER 11-14: U1FRMH: USB FRAME NUMBER HIGH REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — — FRMH<2:0> Legend: R
PIC32MX330/350/370/430/450/470 REGISTER 11-16: U1SOF: USB SOF THRESHOLD REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT<7:0> Legend: R = Rea
PIC32MX330/350/370/430/450/470 REGISTER 11-18: U1BDTP2: USB BDT PAGE 2 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BDTPTRH<23:16> Legend: R
PIC32MX330/350/370/430/450/470 REGISTER 11-20: U1CNFG1: USB CONFIGURATION 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 UTEYE UOEMON — USBSIDL —
PIC32MX330/350/370/430/450/470 REGISTER 11-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPD RETRYDIS —
PIC32MX330/350/370/430/450/470 NOTES: DS60001185C-page 168 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 12.0 I/O PORTS General purpose I/O pins are the simplest of peripherals. They allow the PIC® MCU to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin.
PIC32MX330/350/370/430/450/470 12.1 Parallel I/O (PIO) Ports All port pins have ten registers directly associated with their operation as digital I/O. The data direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx) read the latch. Writes to the latch write the latch.
PIC32MX330/350/370/430/450/470 12.3 Peripheral Pin Select A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The challenge is even greater on low pin count devices. In an application where more than one peripheral needs to be assigned to a single pin, inconvenient workarounds in application code or a complete redesign may be the only options.
PIC32MX330/350/370/430/450/470 TABLE 12-1: INPUT PIN SELECTION [pin name]R Value to RPn Pin Selection Peripheral Pin [pin name]R SFR [pin name]R bits INT3 INT3R INT3R<3:0> T2CK T2CKR T2CKR<3:0> IC3 IC3R IC3R<3:0> U1RX U1RXR U1RXR<3:0> U2RX U2RXR U2RXR<3:0> U5CTS U5CTSR U5CTSR<3:0> REFCLKI REFCLKIR REFCLKIR<3:0> INT4 INT4R INT4R<3:0> T5CK T5CKR T5CKR<3:0> IC4 IC4R IC4R<3:0> U3RX U3RXR U3RXR<3:0> U4CTS U4CTSR U4CTSR<3:0> SDI1 SDI1R SDI1R<3:0> SDI2 SDI2R SDI2R<3:0>
PIC32MX330/350/370/430/450/470 TABLE 12-1: INPUT PIN SELECTION (CONTINUED) Peripheral Pin [pin name]R SFR [pin name]R bits INT1 INT1R INT1R<3:0> T3CK T3CKR T3CKR<3:0> IC1 IC1R IC1R<3:0> U3CTS U3CTSR U3CTSR<3:0> U4RX U4RXR U4RXR<3:0> U5RX U5RXR U5RXR<3:0> SS2 SS2R SS2R<3:0> OCFA OCFAR OCFAR<3:0> Note 1: 2: 3: 4: [pin name]R Value to RPn Pin Selection 0000 = RPD1 0001 = RPG9 0010 = RPB14 0011 = RPD0 0100 = RPD8 0101 = RPB6 0110 = RPD5 0111 = RPB2 1000 = RPF3(4) 1001 = RPF13(3) 10
PIC32MX330/350/370/430/450/470 12.3.5 OUTPUT MAPPING 12.3.6.1 In contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPnR registers (Register 12-2) are used to control output mapping. Like the [pin name]R registers, each register contains sets of 4 bit fields.
PIC32MX330/350/370/430/450/470 TABLE 12-2: OUTPUT PIN SELECTION RPn Port Pin RPnR SFR RPnR bits RPD2 RPD2R RPD2R<3:0> RPG8 RPG8R RPG8R<3:0> RPF4 RPF4R RPF4R<3:0> RPD10 RPD10R RPD10R<3:0> RPF1 RPF1R RPF1R<3:0> RPB9 RPB9R RPB9R<3:0> RPB10 RPB10R RPB10R<3:0> RPC14 RPC14R RPC14R<3:0> RPB5 RPB5R RPB5R<3:0> RPC1(4) RPC1R RPC1R<3:0> RPD14(4) RPD14R RPD14R<3:0> RPG1(4) RPG1R RPG1R<3:0> RPA14(4) RPA14R RPA14R<3:0> RPD3 RPD3R RPD3R<3:0> RPG7 RPG7R RPG7R<3:0> RPF5 RPF
PIC32MX330/350/370/430/450/470 TABLE 12-2: OUTPUT PIN SELECTION (CONTINUED) RPn Port Pin RPnR SFR RPnR bits RPD9 RPD9R RPD9R<3:0> RPG6 RPG6R RPG6R<3:0> RPB8 RPB8R RPB8R<3:0> RPB15 RPB15R RPB15R<3:0> RPD4 RPD4R RPD4R<3:0> RPB0 RPB0R RPB0R<3:0> RPE3 RPE3R RPE3R<3:0> RPB7 RPB7R RPB7R<3:0> RPB2 RPB2R RPB2R<3:0> RPF12(4) RPF12R RPF12R<3:0> (4) RPD12R RPD12R<3:0> RPD12 RPF8(4) RPF8R RPF8R<3:0> RPC3(4) RPC3R RPC3R<3:0> RPE9(4) RPE9R RPE9R<3:0> RPD1 RPD1R RPD1R<3:0>
PIC32MX330/350/370/430/450/470 12.
PIC32MX330/350/370/430/450/470 REGISTER 12-3: Bit Range 31:24 23:16 15:8 7:0 CNCONx: CHANGE NOTICE CONTROL FOR PORTx REGISTER (x = A – G) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 U-0 — — — — R/W-0 U-0 — R/W-0 U-0 U-0 U-0 U-0 U-0 ON — SIDL — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — —
PIC32MX330/350/370/430/450/470 13.0 TIMER1 This family of PIC32 devices features one synchronous/ asynchronous 16-bit timer that can operate as a freerunning interval timer for various timing applications and counting external events. This timer can also be used with the Low-Power Secondary Oscillator (SOSC) for Real-Time Clock (RTC) applications. The following modes are supported: Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices.
PIC32MX330/350/370/430/450/470 13.
PIC32MX330/350/370/430/450/470 REGISTER 13-1: T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED) bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit When TCS = 1: 1 = External clock input is synchronized 0 = External clock input is not synchronized When TCS = 0: This bit is ignored.
PIC32MX330/350/370/430/450/470 NOTES: DS60001185C-page 182 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 14.0 TIMER2/3, TIMER4/5 Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14.
PIC32MX330/350/370/430/450/470 TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)(1) FIGURE 14-2: Data Bus<31:0> <31:0> Reset TMRy(1) MS Half Word ADC Event Trigger(2) Equal Sync LS Half Word 32-bit Comparator PRy TyIF Event Flag TMRx(1) PRx 0 1 TGATE Q D TGATE Q TCS ON TxCK x1 Gate Sync PBCLK 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS Note 1: 2: In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the use of ‘y’ in registers, TyCON,
PIC32MX330/350/370/430/450/470 14.
PIC32MX330/350/370/430/450/470 REGISTER 14-1: TXCON: TYPE B TIMER CONTROL REGISTER (CONTINUED) bit 3 T32: 32-Bit Timer Mode Select bit(2) 1 = Odd numbered and even numbered timers form a 32-bit timer 0 = Odd numbered and even numbered timers form a separate 16-bit timer bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timer Clock Source Select bit(3) 1 = External clock from TxCK pin 0 = Internal peripheral clock bit 0 Unimplemented: Read as ‘0’ Note 1: When using 1:1 PBCLK divisor, the user’s software
PIC32MX330/350/370/430/450/470 15.0 INPUT CAPTURE - Capture timer value on every rising edge of input at ICx pin - Capture timer value on every edge (rising and falling) - Capture timer value on every edge (rising and falling), specified edge first.
PIC32MX330/350/370/430/450/470 15.
PIC32MX330/350/370/430/450/470 REGISTER 15-1: bit 2-0 Note 1: ICXCON: INPUT CAPTURE ‘X’ CONTROL REGISTER (CONTINUED) ICM<2:0>: Input Capture Mode Select bits 111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode) 110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter 101 = Prescaled Capture Event mode – every sixteenth rising edge 100 = Prescaled Capture Event mode – every fourth rising edge 011 = Simple Capture Event mode – every rising edge 010
PIC32MX330/350/370/430/450/470 NOTES: DS60001185C-page 190 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 16.0 OUTPUT COMPARE The Output Compare module is used to generate a single pulse or a train of pulses in response to selected time base events. For all modes of operation, the Output Compare module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. When a match occurs, the Output Compare module generates an event based on the selected mode of operation.
PIC32MX330/350/370/430/450/470 16.
PIC32MX330/350/370/430/450/470 17.0 SERIAL PERIPHERAL INTERFACE (SPI) The SPI module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, Shift registers, display drivers, Analog-to-Digital Converters (ADC), etc. The PIC32 SPI module is compatible with Motorola® SPI and SIOP interfaces.
PIC32MX330/350/370/430/450/470 17.
PIC32MX330/350/370/430/450/470 REGISTER 17-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED) bit 22-18 Unimplemented: Read as ‘0’ bit 17 SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only) 1 = Frame synchronization pulse coincides with the first bit clock 0 = Frame synchronization pulse precedes the first bit clock bit 16 ENHBUF: Enhanced Buffer Enable bit(2) 1 = Enhanced Buffer mode is enabled 0 = Enhanced Buffer mode is disabled bit 15 ON: SPI Peripheral On bit(1) 1 = SPI Peripheral is enabled 0 =
PIC32MX330/350/370/430/450/470 REGISTER 17-1: bit 5 SPIxCON: SPI CONTROL REGISTER (CONTINUED) MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode DISSDI: Disable SDI bit 1 = SDI pin is not used by the SPI module (pin is controlled by PORT function) 0 = SDI pin is controlled by the SPI module STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits 11 = Interrupt is generated when the buffer is not full (has one or more empty elements) 10 = Interrupt is generated when the buffer is empty by one
PIC32MX330/350/370/430/450/470 REGISTER 17-2: Bit Range 31:24 23:16 15:8 7:0 SPIxCON2: SPI CONTROL REGISTER 2 Bit 31/23/15/7 Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — U-0 — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPISGNEXT — — FRMERREN SPIROVEN R/W-0 U-0 U-0 U-0 R/W-0 U-0 AUDEN(1) — — — AUDMONO
PIC32MX330/350/370/430/450/470 REGISTER 17-3: Bit Range 31:24 23:16 15:8 7:0 SPIxSTAT: SPI STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 — — — U-0 U-0 U-0 R-0 R-0 — — — U-0 U-0 U-0 R/C-0, HS R-0 U-0 U-0 R-0 — — — FRMERR SPIBUSY — — SPITUR RXBUFELM<4:0> R-0 R-0 R-0 TXBUFELM<4:0> R-0 R/W-0 R-0 U-0 R-1 U-0 R-0 R-0 SRMT SPIROV SPIRBE
PIC32MX330/350/370/430/450/470 REGISTER 17-3: SPIxSTAT: SPI STATUS REGISTER (CONTINUED) bit 3 SPITBE: SPI Transmit Buffer Empty Status bit 1 = Transmit buffer, SPIxTXB is empty 0 = Transmit buffer, SPIxTXB is not empty Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR. Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.
PIC32MX330/350/370/430/450/470 NOTES: DS60001185C-page 200 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 18.0 INTER-INTEGRATED CIRCUIT™ (I2C™) Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/ 430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. “Inter-Integrated Circuit™ (I2C™)” (DS60001116) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX330/350/370/430/450/470 FIGURE 18-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2CxRCV Read SCLx Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read PBCLK DS60001185C-page 202 2012-2013 Mi
PIC32MX330/350/370/430/450/470 18.
PIC32MX330/350/370/430/450/470 REGISTER 18-1: I2CXCON: I2C™ CONTROL REGISTER (CONTINUED) bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit.
PIC32MX330/350/370/430/450/470 REGISTER 18-2: Bit Range 31:24 23:16 15:8 7:0 I2CXSTAT: I2C™ STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0, HSC R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 R/C-0, HS R/C-0, HS R-0, HSC R/C-0
PIC32MX330/350/370/430/450/470 REGISTER 18-2: I2CXSTAT: I2C™ STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected.
PIC32MX330/350/370/430/450/470 19.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX330/350/370/430/450/470 19.
PIC32MX330/350/370/430/450/470 REGISTER 19-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character – requires reception of Sync character (0x55); cleared by hardware upon completion 0 = Baud rate measurement disabled or completed bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode – 4x baud clock enabled 0 = Standard Speed
PIC32MX330/350/370/430/450/470 REGISTER 19-2: Bit Range 31:24 23:16 15:8 7:0 UxSTA: UARTx STATUS AND CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — ADM_EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<7:0> R/W-0 R/W-0 UTXISEL<1:0> R/W-0 R/W-0 URXISEL<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-1 UTXINV URXEN UTXBRK UTXEN UTXBF
PIC32MX330/350/370/430/450/470 REGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 8 TRMT: Transmit Shift Register is Empty bit (read-only) 1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit 11 = Reserved; do not use 10 = Interrupt flag bit is asserted while receive buf
PIC32MX330/350/370/430/450/470 19.2 Timing Diagrams Figure 19-2 and Figure 19-3 illustrate typical receive and transmit timing for the UART module.
PIC32MX330/350/370/430/450/470 20.0 PARALLEL MASTER PORT (PMP) Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. “Parallel Master Port (PMP)” (DS60001128) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX330/350/370/430/450/470 20.
PIC32MX330/350/370/430/450/470 REGISTER 20-1: bit 4 bit 3 bit 2 bit 1 bit 0 PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) CS2P: Chip Select 0 Polarity bit(2) 1 = Active-high (PMCS2) 0 = Active-low (PMCS2) CS1P: Chip Select 0 Polarity bit(2) 1 = Active-high (PMCS1) 0 = Active-low (PMCS1) Unimplemented: Read as ‘0’ WRSP: Write Strobe Polarity bit For Slave Modes and Master mode 2 (MODE<1:0> = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode 1 (MODE<1:0
PIC32MX330/350/370/430/450/470 REGISTER 20-2: Bit Range 31:24 23:16 15:8 PMMODE: PARALLEL PORT MODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUSY R/W-0 7:0 IRQM<1:0> R/W-0 R/W-0 WAITB<1:0>(1) INCM<1:0> R/W-0 MODE16 R/W-0 MODE<
PIC32MX330/350/370/430/450/470 REGISTER 20-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED) bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits(1) 1111 = Wait of 16 TPB • • • 0001 = Wait of 2 TPB 0000 = Wait of 1 TPB (default) bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits(1) 11 = Wait of 4 TPB 10 = Wait of 3 TPB 01 = Wait of 2 TPB 00 = Wait of 1 TPB (default) For Read operations: 11 = Wait of 3 TPB 10 = Wait of 2 TPB 01 = Wait of 1 TPB 00 = Wait of 0 TPB (default) No
PIC32MX330/350/370/430/450/470 REGISTER 20-3: Bit Range 31:24 23:16 15:8 PMADDR: PARALLEL PORT ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 (1) R/W-0 (3) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — R/W-0 R/W-0 R/W-0 CS2 CS1 (2) ADDR15 7:0 R/W-0 ADDR14(4) R/W-0 ADDR<
PIC32MX330/350/370/430/450/470 REGISTER 20-4: Bit Range 31:24 23:16 15:8 7:0 PMAEN: PARALLEL PORT PIN ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN<15:14>(1) R/W-0 R/W-0 PTEN<13:8> R/W-0 R/W-0 R/W-0 R/W-0
PIC32MX330/350/370/430/450/470 REGISTER 20-5: Bit Range 31:24 23:16 15:8 7:0 PMSTAT: PARALLEL PORT STATUS REGISTER (SLAVE MODES ONLY) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R/W-0, HSC U-0 U-0 R-0 R-0 R-0 R-0 IBF IBOV — — IB3F IB2F IB1F IB0F R-1 R/W-0, HSC U-0 U-0 R-1 R-
PIC32MX330/350/370/430/450/470 21.0 REAL-TIME CLOCK AND CALENDAR (RTCC) Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. “RealTime Clock and Calendar (RTCC)” (DS60001125) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX330/350/370/430/450/470 21.
PIC32MX330/350/370/430/450/470 REGISTER 21-1: RTCCON: RTC CONTROL REGISTER (CONTINUED) RTCWREN: RTC Value Registers Write Enable bit(4) 1 = RTC Value registers can be written to by the user 0 = RTC Value registers are locked out from being written to by the user RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data read If the register is read twice and results in the same data, the data can be assu
PIC32MX330/350/370/430/450/470 REGISTER 21-2: Bit Range 31:24 23:16 15:8 7:0 RTCALRM: RTC ALARM CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R-0 R/W-0 R/W-0 CHIME(2) R/W-0 (3) R/W-0 ALRMEN(1,2) R/W-0 (2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PIV ALRMSYNC(3)
PIC32MX330/350/370/430/450/470 REGISTER 21-2: RTCALRM: RTC ALARM CONTROL REGISTER (CONTINUED) ARPT<7:0>: Alarm Repeat Counter Value bits(3) 11111111 = Alarm will trigger 256 times bit 7-0 • • • 00000000 = Alarm will trigger one time The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1. Note 1: 2: 3: Note: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0.
PIC32MX330/350/370/430/450/470 REGISTER 21-3: Bit Range 31:24 23:16 15:8 7:0 RTCTIME: RTC TIME VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10<3:0> R/W-x R/W-x HR01<3:0> R/W-x R/W-x R/W-x R/W-x MIN10<3:0> R/W-x R/W-x R/W-x R/W-x R/W-x MIN01<3:0> R/W-x R/W-x R/W-x SEC10<3:0> R/W-x R/W-x SEC01<3:0> U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
PIC32MX330/350/370/430/450/470 REGISTER 21-4: Bit Range 31:24 23:16 15:8 7:0 RTCDATE: RTC DATE VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YEAR10<3:0> R/W-x R/W-x R/W-x R/W-x R/W-x YEAR01<3:0> R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x MONTH10<3:0> R/W-x R/W-x R/W-x MONTH01<3:0> DAY10<3:0> R/W-x R/W-x DAY01<3:0> U-0 U-0 U-0 U-0 — — — —
PIC32MX330/350/370/430/450/470 REGISTER 21-5: Bit Range 31:24 23:16 15:8 7:0 ALRMTIME: ALARM TIME VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10<3:0> R/W-x R/W-x HR01<3:0> R/W-x R/W-x R/W-x R/W-x MIN10<3:0> R/W-x R/W-x R/W-x R/W-x R/W-x MIN01<3:0> R/W-x R/W-x R/W-x SEC10<3:0> R/W-x R/W-x SEC01<3:0> U-0 U-0 U-0 U-0 U-0 U-0 U-0 U
PIC32MX330/350/370/430/450/470 REGISTER 21-6: Bit Range 31:24 23:16 15:8 7:0 ALRMDATE: ALARM DATE VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 — — R/W-x R/W-x R/W-x R/W-x — R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x MONTH10<3:0> R/W-x MONTH01<3:0> DAY10<1:0> R/W-x R/W-x DAY01<3:0> U-0 U-0 U-0 U-0 — — — — R/W-x R/W-x
PIC32MX330/350/370/430/450/470 NOTES: DS60001185C-page 230 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 22.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS60001104) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX330/350/370/430/450/470 FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADRC FRC(1) Div 2 1 TAD ADCS<7:0> 0 8 TPB ADC Conversion Clock Multiplier (2) 2, 4,..., 512 Note 1: 2: See Section 30.0 “Electrical Characteristics” for the exact FRC clock value. Refer to Figure 8-1 in Section 8.0 “Oscillator Configuration” for more information. DS60001185C-page 232 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 22.
PIC32MX330/350/370/430/450/470 REGISTER 22-1: bit 4 AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED) CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated) 1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the ADC interrupt is generated.
PIC32MX330/350/370/430/450/470 REGISTER 22-2: Bit Range 31:24 23:16 15:8 AD1CON2: ADC CONTROL REGISTER 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 OFFCAL — CSCNA — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFM ALTS VCFG<2:0> 7:0 Bit Bit 28/20/12/4 27/19/11/3 R-0 U-0 BUFS
PIC32MX330/350/370/430/450/470 REGISTER 22-3: Bit Range 31:24 23:16 15:8 7:0 AD1CON3: ADC CONTROL REGISTER 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC — — R/W-0 R/W-0 R/W-0 R/W R/W-0 SAMC<4:0>(1) R/W-0 R/W-0 (2) R/W-0 ADCS<7:0> Le
PIC32MX330/350/370/430/450/470 REGISTER 22-4: Bit Range 31:24 23:16 15:8 7:0 AD1CHS: ADC INPUT SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 U-0 U-0 CH0NB — — Bit Bit 28/20/12/4 27/19/11/3 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 CH0SB<4:0> R/W-0 U-0 U-0 CH0NA — — R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — CH0SA
PIC32MX330/350/370/430/450/470 REGISTER 22-5: Bit Range 31:24 23:16 15:8 7:0 AD1CSSL: ADC INPUT SCAN SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CSSL30 CSSL29 CSSL28 CSSL27 CSSL26 CSSL25 CSSL24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL23 CSSL21 CSSL21 CSSL20 CSSL19 CSSL18 CSSL17 CSSL16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MX330/350/370/430/450/470 23.0 COMPARATOR The Analog Comparator module contains two comparators that can be configured in a variety of ways. Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. “Comparator” (DS60001110) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.
PIC32MX330/350/370/430/450/470 23.
PIC32MX330/350/370/430/450/470 REGISTER 23-2: Bit Range 31:24 23:16 15:8 7:0 CMSTAT: COMPARATOR STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — SIDL — — — — — U-0 U-0 U-0 U-0 U-0 U-0 R-0 R-0 — — — — — — C2OUT C1OUT Legen
PIC32MX330/350/370/430/450/470 NOTES: DS60001185C-page 242 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 24.0 COMPARATOR VOLTAGE REFERENCE (CVREF) The CVREF module is a 16-tap, resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source.
PIC32MX330/350/370/430/450/470 24.
PIC32MX330/350/370/430/450/470 25.0 CHARGE TIME MEASUREMENT UNIT (CTMU) other on-chip analog modules, the CTMU can be used for high resolution time measurement, measure capacitance, measure relative changes in capacitance or generate output pulses with a specific time delay. The CTMU is ideal for interfacing with capacitive-based sensors. Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/ 450/470 family of devices. It is not intended to be a comprehensive reference source.
PIC32MX330/350/370/430/450/470 25.
PIC32MX330/350/370/430/450/470 REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 24 EDG1STAT: Edge 1 Status bit Indicates the status of Edge 1 and can be written to control edge source 1 = Edge 1 has occurred 0 = Edge 1 has not occurred bit 23 EDG2MOD: Edge 2 Edge Sampling Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive bit 22 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 programmed for a positive edge response 0 = Edge 2 programmed for a negative edge response bit 21-18
PIC32MX330/350/370/430/450/470 REGISTER 25-1: bit 10 CTMUCON: CTMU CONTROL REGISTER (CONTINUED) EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 must occur before Edge 2 can occur 0 = No edge sequence is needed IDISSEN: Analog Current Source Control bit(2) 1 = Analog current source output is grounded 0 = Analog current source output is not grounded CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change fro
PIC32MX330/350/370/430/450/470 26.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “PowerSaving Features” (DS60001130) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX330/350/370/430/450/470 The processor will exit, or ‘wake-up’, from Sleep on one of the following events: • On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority. • On any form of device Reset • On a WDT time-out If the interrupt priority is lower than or equal to the current priority, the CPU will remain Halted, but the PBCLK will start running and the device will enter into Idle mode. 26.3.
PIC32MX330/350/370/430/450/470 26.4 Peripheral Module Disable To disable a peripheral, the associated PMDx bit must be set to ‘1’. To enable a peripheral, the associated PMDx bit must be cleared (default). See Table 26-1 for more information. The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module.
PIC32MX330/350/370/430/450/470 26.4.1 CONTROLLING CONFIGURATION CHANGES Because peripherals can be disabled during run time, some restrictions on disabling peripherals are needed to prevent accidental configuration changes. PIC32 devices include two features to prevent alterations to enabled or disabled peripherals: • Control register lock sequence • Configuration bit select lock 26.4.1.1 Control Register Lock Under normal operation, writes to the PMDx registers are not allowed.
PIC32MX330/350/370/430/450/470 27.0 SPECIAL FEATURES 27.1 Configuration Bits The Configuration bits can be programmed using the following registers to select various device configurations. Note 1: This data sheet summarizes the features of the PIC32MX330/350/370/ 430/450/470 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog Timer and Power-up Timer” (DS60001114), Section 32.
PIC32MX330/350/370/430/450/470 REGISTER 27-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED) bit 24 BWP: Boot Flash Write-Protect bit Prevents boot Flash memory from being modified during code execution. 1 = Boot Flash is writable 0 = Boot Flash is not writable bit 23-20 Reserved: Write ‘1’ bit 19-12 PWP<7:0>: Program Flash Write-Protect bits Prevents selected program Flash memory pages from being modified during code execution.
PIC32MX330/350/370/430/450/470 REGISTER 27-2: Bit Range 31:24 23:16 15:8 7:0 DEVCFG1: DEVICE CONFIGURATION WORD 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — R/P R/P r-1 R/P R/P R/P FWDTEN WINDIS — R/P R/P R/P R/P r-1 R/P — OSCIOFNC R/P FCKSM<1:0> Bit 25/17/9/1 Bit 24/16/8/0 R/P R/P FWDTWINSZ<1:0> R/P R/P R/P R/P WDTPS<4:0> FPBDIV<1:0> R/P r-1 R/P r-1 r-1 IESO — FSOSCEN —
PIC32MX330/350/370/430/450/470 REGISTER 27-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED) bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK div
PIC32MX330/350/370/430/450/470 REGISTER 27-3: Bit Range 31:24 23:16 15:8 7:0 DEVCFG2: DEVICE CONFIGURATION WORD 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — r-1 r-1 r-1 r-1 r-1 R/P R/P R/P — — — — — R/P r-1 r-1 r-1 r-1 UPLLEN(1) — — — — r-1 R/P-1 R/P R/P-1 r-1 — FPLLMUL<2:0> FPLLODIV<2:0> R/P R/P R/P UPLLIDIV<2:0>(1) R/P — R/P
PIC32MX330/350/370/430/450/470 REGISTER 27-3: DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED) bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider Note 1: This bit is available on PIC32MX4XX devices only. DS60001185C-page 258 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 REGISTER 27-4: Bit Range 31:24 23:16 15:8 7:0 DEVCFG3: DEVICE CONFIGURATION WORD 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/P R/P R/P R/P U-0 U-0 U-0 FVBUSONIO FUSBIDIO IOL1WAY PMDL1WAY — — — — U-0 U-0 U-0 U-0 U-0 R/P R/P R/P — — — — — R/P R/P R/P R/P R/P FSRSSEL<2:0> R/P R/P R/P R/P R/P R/P USERID<15:8> R/P R/P Legend: R = Readable bit -n = Valu
PIC32MX330/350/370/430/450/470 REGISTER 27-5: Bit Range 31:24 23:16 15:8 7:0 CFGCON: CONFIGURATION CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-1 — — — — JTAGEN TROEN — TD
PIC32MX330/350/370/430/450/470 REGISTER 27-6: Bit Range 31:24 23:16 15:8 7:0 DEVID: DEVICE AND REVISION ID REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R R R R R VER<3:0>(1) R R R R R R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R DEVID<27:24>(1) R R (1) DEVID<23:16> R R R R R R R R R R R DEVID<15:8>(1) R R R R DEVID<7:0> R (1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR
PIC32MX330/350/370/430/450/470 27.2 Watchdog Timer (WDT) This section describes the operation of the WDT and Power-up Timer of the PIC32MX330/350/370/430/450/ 470. The WDT, when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler.
PIC32MX330/350/370/430/450/470 REGISTER 27-7: Bit Range 31:24 23:16 15:8 7:0 WDTCON: WATCHDOG TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — R-y R-y R-y R-y R-y R/W-0 R/W-0 R/W-0 (1,2) ON U-0 — SWDTPS<4:0> WDTWIN
PIC32MX330/350/370/430/450/470 27.3 On-Chip Voltage Regulator All PIC32MX330/350/370/430/450/470 devices’ core and digital logic are designed to operate at a nominal 1.8V. To simplify system designs, most devices in the PIC32MX330/350/370/430/450/470 family incorporate an on-chip regulator providing the required core logic voltage from VDD. A low-ESR capacitor (such as tantalum) must be connected to the VCAP pin (see Figure 27-2). This helps to maintain the stability of the regulator.
PIC32MX330/350/370/430/450/470 28.0 INSTRUCTION SET The PIC32MX330/350/370/430/450/470 family instruction set complies with the MIPS32® Release 2 instruction set architecture. The PIC32 device family does not support the following features: • Core extend instructions • Coprocessor 1 instructions • Coprocessor 2 instructions Note: Refer to “MIPS32® Architecture for Programmers Volume II: The MIPS32® Instruction Set” at www.imgtec.com for more information. 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 NOTES: DS60001185C-page 266 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 29.
PIC32MX330/350/370/430/450/470 29.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE.
PIC32MX330/350/370/430/450/470 29.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC32MX330/350/370/430/450/470 29.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification.
PIC32MX330/350/370/430/450/470 30.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC32MX330/350/370/430/450/470 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX330/350/370/430/450/470 devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
PIC32MX330/350/370/430/450/470 30.1 DC Characteristics TABLE 30-1: OPERATING MIPS VS. VOLTAGE VDD Range (in Volts) Characteristic DC5 DC5b Note 1: Max. Frequency Temp. Range (in °C) PIC32MX330/350/370/430/450/470 2.3-3.6V (1) -40°C to +85°C 100 MHz 2.3-3.6V (1) -40°C to +105°C 80 MHz Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN.
PIC32MX330/350/370/430/450/470 TABLE 30-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical Max. Units Conditions Operating Voltage DC10 VDD Supply Voltage 2.3 — 3.6 V — DC12 VDR RAM Data Retention Voltage (Note 1) 1.
PIC32MX330/350/370/430/450/470 TABLE 30-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp DC CHARACTERISTICS Parameter No. Typical(3) Maximum Units Conditions 4 mA 4 MHz Operating Current (IDD)(1,2) DC20 2.
PIC32MX330/350/370/430/450/470 TABLE 30-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp DC CHARACTERISTICS Parameter No. Typical(2) Maximum Units Conditions Idle Current (IIDLE): Core Off, Clock on Base Current (Note 1) DC30a 1 2.
PIC32MX330/350/370/430/450/470 TABLE 30-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) DC CHARACTERISTICS Param. Typical(2) Maximum No. Standard Operating Conditions: 2.3V to 3.
PIC32MX330/350/370/430/450/470 TABLE 30-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param. Symb. No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp Min. Typ.(1) Max. Units DI18 Input Low Voltage I/O Pins with PMP I/O Pins SDAx, SCLx VSS VSS VSS — — — 0.15 VDD 0.2 VDD 0.3 VDD V V V DI19 SDAx, SCLx VSS — 0.8 V 0.65 VDD 0.25 VDD + 0.8V — — VDD 5.
PIC32MX330/350/370/430/450/470 TABLE 30-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) DC CHARACTERISTICS Param. Symb. No. DI50 DI51 IIL Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp Min. Typ.(1) Max.
PIC32MX330/350/370/430/450/470 TABLE 30-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) DC CHARACTERISTICS Param. Symb. No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp Min. Typ.(1) Max. Units Conditions Pins with Analog functions. Exceptions: [SOSCI] = 0 mA max. Digital 5V tolerant desigInput High Injection nated pins (VIH < 5.5V)(9).
PIC32MX330/350/370/430/450/470 TABLE 30-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp DC CHARACTERISTICS Param.
PIC32MX330/350/370/430/450/470 TABLE 30-10: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp DC CHARACTERISTICS Param. Symbol No. BO10 Note 1: VBOR Characteristics BOR Event on VDD transition high-to-low Min.(1) Typical 2.0 — Max. Units Conditions 2.3 V — Parameters are for design guidance only and are not tested in manufacturing.
PIC32MX330/350/370/430/450/470 TABLE 30-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical(1) Max. Units Conditions 20,000 — — E/W — Program Flash Memory(3) D130 EP Cell Endurance D131 VPR VDD for Read 2.3 — 3.6 V — D132 VPEW VDD for Erase or Write 2.3 — 3.
PIC32MX330/350/370/430/450/470 TABLE 30-14: COMPARATOR SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical Max. Units Comments D300 VIOFF Input Offset Voltage — ±7.
PIC32MX330/350/370/430/450/470 30.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MX330/350/370/430/450/470 AC characteristics and timing parameters.
PIC32MX330/350/370/430/450/470 TABLE 30-17: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. Symbol No. OS10 FOSC OS11 Min. Typical(1) Max.
PIC32MX330/350/370/430/450/470 TABLE 30-18: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical Max. Units Conditions OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range 3.
PIC32MX330/350/370/430/450/470 FIGURE 30-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Note: Refer to Figure 30-1 for load conditions. DO31 DO32 TABLE 30-21: I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. No. DO31 DO32 Symbol TIOR TIOF Characteristics(2) Port Output Rise Time Port Output Fall Time Min.
PIC32MX330/350/370/430/450/470 FIGURE 30-4: POWER-ON RESET TIMING CHARACTERISTICS Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) CPU Starts Fetching Code SY00 (TPU) (Note 1) Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) SY00 (TPU) (Note 1) Note 1: 2: SY10 (TOST) CPU Starts Fetching Code The power-up per
PIC32MX330/350/370/430/450/470 FIGURE 30-5: EXTERNAL RESET TIMING CHARACTERISTICS Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) MCLR TMCLR (SY20) BOR TBOR (SY30) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code TOST (SY10) TABLE 30-22: RESETS TIMING Standard Operating Conditions: 2.3V to 3.
PIC32MX330/350/370/430/450/470 FIGURE 30-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRx Note: Refer to Figure 30-1 for load conditions. TABLE 30-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. No.
PIC32MX330/350/370/430/450/470 TABLE 30-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Max. Units Conditions TB10 TTXH TxCK Synchronous, with High Time prescaler [(12.
PIC32MX330/350/370/430/450/470 FIGURE 30-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM mode) OC10 OC11 Note: Refer to Figure 30-1 for load conditions. TABLE 30-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical(2) Max.
PIC32MX330/350/370/430/450/470 FIGURE 30-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 SP31 SDIx MSb In LSb SP30 LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 30-1 for load conditions. TABLE 30-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX330/350/370/430/450/470 FIGURE 30-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SCKX (CKP = 1) SP10 SP21 SP20 SP20 SP21 SP35 LSb Bit 14 - - - - - -1 MSb SDOX SP30,SP31 SDIX MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 30-1 for load conditions. TABLE 30-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX330/350/370/430/450/470 FIGURE 30-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX LSb Bit 14 - - - - - -1 SP51 SP30,SP31 SDIX MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 30-1 for load conditions. TABLE 30-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX330/350/370/430/450/470 FIGURE 30-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In SP40 SP51 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 30-1 for load conditions. TABLE 30-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX330/350/370/430/450/470 TABLE 30-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max.
PIC32MX330/350/370/430/450/470 FIGURE 30-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 30-1 for load conditions. FIGURE 30-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 30-1 for load conditions. DS60001185C-page 298 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 TABLE 30-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. Symbol No. IM10 IM11 IM20 IM21 IM25 IM26 IM30 IM31 IM33 IM34 Min.(1) Max.
PIC32MX330/350/370/430/450/470 TABLE 30-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. Symbol No. IM40 IM45 TAA:SCL Min.(1) Max.
PIC32MX330/350/370/430/450/470 FIGURE 30-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition Note: Refer to Figure 30-1 for load conditions. FIGURE 30-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out Note: Refer to Figure 30-1 for load conditions. 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 TABLE 30-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. No.
PIC32MX330/350/370/430/450/470 TABLE 30-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. No. IS34 IS40 IS45 IS50 Note 1: Symbol THD:STO TAA:SCL TBF:SDA CB Characteristics Stop Condition Hold Time Min. Max.
PIC32MX330/350/370/430/450/470 TABLE 30-34: ADC MODULE SPECIFICATIONS (5) AC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp Min. Typical Max. Units Conditions Greater of VDD – 0.3 or 2.5 — Lesser of VDD + 0.3 or 3.6 V VSS — VSS + 0.3 V AVSS + 2.0 — AVDD V (Note 1) 2.5 — 3.
PIC32MX330/350/370/430/450/470 TABLE 30-34: ADC MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS(5) Param. No. Symbol Characteristics Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp Min. Typical Max. Units Conditions ADC Accuracy – Measurements with Internal VREF+/VREFAD20d Nr Resolution AD21d INL Integral Nonlinearity > -1 — <1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.
PIC32MX330/350/370/430/450/470 TABLE 30-35: 10-BIT CONVERSION RATE PARAMETERS AC CHARACTERISTICS ADC Input ADC Speed AN0-AN14 1 Msps to 400 ksps(1) Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp (2) TAD Min. Sampling Time Min. 65 ns 132 ns RS Max. ADC Channels Configuration VDD 500 3.0V to 3.6V VREF- VREF+ CHX ANx Up to 400 ksps 200 ns 200 ns SHA 5.0 k 2.5V to 3.
PIC32MX330/350/370/430/450/470 TABLE 30-36: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. Symbol No. Min. Typical(1) Max.
PIC32MX330/350/370/430/450/470 FIGURE 30-18: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 TSAMP AD55 AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets ADxCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 17.
PIC32MX330/350/370/430/450/470 FIGURE 30-19: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Execution Set ADON SAMP ch0_dischrg ch0_samp eoc TSAMP AD55 TSAMP AD55 TCONV CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 1 – Software sets ADxCON. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period. TSAMP is described in Section 17.
PIC32MX330/350/370/430/450/470 FIGURE 30-20: PARALLEL SLAVE PORT TIMING CS PS5 RD PS6 WR PS4 PS7 PMD<7:0> PS1 PS3 PS2 TABLE 30-37: PARALLEL SLAVE PORT REQUIREMENTS AC CHARACTERISTICS Para Symbol m.No. Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp Min. Typ. Max.
PIC32MX330/350/370/430/450/470 FIGURE 30-21: PARALLEL MASTER PORT READ TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock PM4 Address PMA<13:18> PM6 PMD<7:0> Data Data Address<7:0> Address<7:0> PM2 PM7 PM3 PMRD PM5 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 30-38: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX330/350/370/430/450/470 FIGURE 30-22: PARALLEL MASTER PORT WRITE TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock Address PMA<13:18> PM2 + PM3 Address<7:0> PMD<7:0> Data PM12 PM13 PMRD PM11 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 30-39: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. Symbol No.
PIC32MX330/350/370/430/450/470 TABLE 30-40: OTG ELECTRICAL SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) USB313 VUSB3V3 USB Voltage Min. Typ. Max. Units 3.0 — 3.6 V Conditions Voltage on VUSB3V3 must be in this range for proper USB operation USB315 VILUSB Input Low Voltage for USB Buffer — — 0.
PIC32MX330/350/370/430/450/470 TABLE 30-41: CTMU CURRENT SOURCE SPECIFICATIONS DC CHARACTERISTICS Param No. Symbol Characteristic Standard Operating Conditions:2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp Min. Typ. Max. Units Conditions CTMU CURRENT SOURCE CTMUI1 IOUT1 Base Range(1) — 0.55 — µA CTMUICON<9:8> = 01 CTMUI2 IOUT2 10x Range(1) — 5.
PIC32MX330/350/370/430/450/470 FIGURE 30-23: EJTAG TIMING CHARACTERISTICS TTCKcyc TTCKhigh TTCKlow Trf TCK Trf TMS TDI TTsetup TThold Trf Trf TDO TRST* TTRST*low TTDOout TTDOzstate Defined Trf Undefined TABLE 30-42: EJTAG TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. No. Symbol Description(1) Min. Max.
PIC32MX330/350/370/430/450/470 NOTES: DS60001185C-page 316 2012-2013 Microchip Technology Inc.
DC AND AC DEVICE CHARACTERISTICS GRAPHS Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. FIGURE 31-1: VOH – 4x DRIVER PINS FIGURE 31-3: Ͳ40.00 45.
TYPICAL IPD CURRENT @ VDD = 3.3V FIGURE 31-7: PIC32MX350/450 DEVICES PIC32MX330/430 DEVICES 400 350 IPD (μA) IPD (μA) 300 250 200 150 100 50 0 Ͳ40 Ͳ30 Ͳ20 Ͳ10 0 10 20 30 40 50 60 70 80 90 100 110 600 550 500 450 400 350 300 250 200 150 100 50 0 Ͳ40 Ͳ30 Ͳ20 Ͳ10 0 Temperature (Celsius) FIGURE 31-6: TYPICAL IPD CURRENT @ VDD = 3.3V TYPICAL IPD CURRENT @ VDD = 3.3V FIGURE 31-8: TYPICAL IIDLE CURRENT @ VDD = 3.
TYPICAL IIDLE CURRENT @ VDD = 3.3V FIGURE 31-11: TYPICAL IDD CURRENT @ VDD = 3.3V PIC32MX330/430 DEVICES PIC32MX350/450 DEVICES 20 60 18 50 14 40 12 IDD (mA) IIDLE CURRENT (mA) 16 10 8 30 20 6 4 10 2 0 0 10 20 30 40 50 60 70 80 90 0 100 0 10 20 30 40 MIPS FIGURE 31-10: TYPICAL IIDLE CURRENT @ VDD = 3.3V FIGURE 31-12: PIC32MX370/470 DEVICES 60 70 80 90 100 TYPICAL IDD CURRENT @ VDD = 3.
TYPICAL IDD CURRENT @ VDD = 3.3V FIGURE 31-15: PIC32MX370/470 DEVICES TYPICAL LPRC FREQUENCY @ VDD = 3.3V 33 60 LPRC Frequency (kHz) 50 IDD (mA) 40 30 20 32 31 10 0 0 10 20 30 40 50 60 70 80 90 100 30 -40 -30 -20 -10 0 10 MIPS FIGURE 31-14: 20 30 40 50 60 70 80 90 100 Temperature (Celsius) TYPICAL FRC FREQUENCY @ VDD = 3.3V FIGURE 31-16: TYPICAL CTMU TEMPERATURE DIODE FORWARD VOLTAGE 7990 0.850 7980 0.800 7970 0.
PIC32MX330/350/370/430/450/470 32.0 PACKAGING INFORMATION 32.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) PIC32MX330F 064H-I/PT XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN e3 0510017 100-Lead TQFP (14x14x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 100-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC32MX330/350/370/430/450/470 32.1 Package Marking Information (Continued) 64-Lead QFN (9x9x0.9 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC32MX330F 064H-I/MR e3 0510017 124-Lead VTLA (9x9x0.9 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...
PIC32MX330/350/370/430/450/470 32.2 Package Details The following sections give the technical details of the packages.
PIC32MX330/350/370/430/450/470 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001185C-page 324 2012-2013 Microchip Technology Inc.
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PIC32MX330/350/370/430/450/470 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001185C-page 326 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 e E E1 N b NOTE 1 1 23 NOTE 2 α c A φ L β A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV A2 L1 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ±
PIC32MX330/350/370/430/450/470 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001185C-page 328 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001185C-page 330 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 DS60001185C-page 332 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 NOTES: DS60001185C-page 334 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 APPENDIX A: REVISION HISTORY Revision A (July 2012) This is the initial released version of the document. Revision B (April 2013) Note: The status of this data sheet was updated to Preliminary; however, any electrical specifications listed for PIC32MX370/470 devices is to be considered Advance Information and is marked accordingly. This revision includes the following updates, as shown in Table A-1.
PIC32MX330/350/370/430/450/470 Revision C (October 2013) This revision includes the following updates, as listed in Table A-2. TABLE A-2: MAJOR SECTION UPDATES Section Update Description “32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM) with Audio/Graphics/Touch (HMI), USB, and Advanced Analog” The Operating Conditions and Core sections were updated in support of 100 MHz (-40ºC to +85ºC) devices. 2.
PIC32MX330/350/370/430/450/470 INDEX A AC Characteristics ............................................................ 284 10-Bit Conversion Rate Parameters ......................... 306 ADC Specifications ................................................... 304 Analog-to-Digital Conversion Requirements............. 307 EJTAG Timing Requirements ................................... 315 Internal FRC Accuracy.............................................. 286 Internal RC Accuracy ................................
PIC32MX330/350/370/430/450/470 O Oscillator Configuration..................................................... 111 Output Compare................................................................ 191 P Packaging ......................................................................... 321 Details ....................................................................... 323 Marking ..................................................................... 321 Parallel Master Port (PMP) ..............................
PIC32MX330/350/370/430/450/470 NVMCON (Programming Control) .............................. 96 NVMDATA (Flash Program Data)............................... 98 NVMKEY (Programming Unlock)................................ 97 NVMSRCADDR (Source Data Address)..................... 98 OCxCON (Output Compare x Control) ..................... 192 OSCCON (Oscillator Control) ................................... 113 PFABT (Prefetch Cache Abort Statistics) ................. 129 PMADDR (Parallel Port Address) ..............
PIC32MX330/350/370/430/450/470 NOTES: DS60001185C-page 340 2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC32MX330/350/370/430/450/470 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MX 3XX F 064 H T - 80 I / PT - XXX Example: PIC32MX330F064H-80I/PT: General purpose PIC32, 32-bit RISC MCU, 64 KB program memory, 64-pin, Industrial temperature, TQFP package.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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