Datasheet
Table Of Contents
- TABLE 1: Silicon DEVREV Values
- TABLE 2: Silicon Issue Summary
- Silicon Errata Issues
- Data Sheet Clarifications
- 1. Module: Table 27-1: Memory Programming Requirements
- 2. Module: Table 27-2: Comparator Specifications
- 3. Module: Table 27-4: Internal Voltage Regulator Specifications
- 4. Module: Section 27.3 “DC Characteristics: PIC18F87J11 Family (Industrial)”
- 5. Module: Example 6-2: Erasing a Flash Program Memory Row
- 6. Module: Section 19.3 “SPI Mode” and Section 19.4 “I2C™ Mode”
- 7. Module: Figure 19-10: I2C™ Slave Mode Timing (Transmission, 7-Bit Address)
- 8. Module: Figure 19-24: I2C™ Master Mode Waveform (Reception, 7-Bit Address)
- 9. Module: Table 1-3: PIC18F6XJ1X Pinout I/O Descriptions
- 10. Module: Memory Organization
- 11. Module: Memory Organization
- 12. Module: Electrical Specification
- Document Revision History
- Worldwide Sales and Service
2011 Microchip Technology Inc. DS80495E-page 9
PIC18F87J11 FAMILY
FIGURE 19-10: I
2
C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
SDAx
SCLx
BF (SSPxSTAT<0>)
A6
A5
A4 A3
A2
A1
D6
D5
D4
D3
D2
D1
D0
1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9
SSPxBUF is written in software
Cleared in software
Data in
sampled
S
ACK
Transmitting Data
R/W = 0
ACK
Receiving Address
A7 D7
9 1
D6
D5
D4
D3
D2
D1
D0
2 3 4 5 6 7 8 9
SSPxBUF is written in software
Cleared in software
From SSPxIF ISR
Transmitting Data
D7
1
CKP (SSPxCON<4>)
P
ACK
CKP is set in software
CKP is set in software
SCLx held low
while CPU
responds to SSPxIF
SSPxIF (PIR1<3> or PIR3<7>)
From SSPxIF ISR
Clear by reading