Datasheet

PIC18F87J11 FAMILY
DS80495E-page 8  2011 Microchip Technology Inc.
5. Module: Example 6-2: Erasing a Flash
Program Memory Row
On page 94, an instruction to enable the write
process to memory for erasing the Flash program-
ming memory row is missing in the example. The
changed content is indicated in bold text in the
following example:
EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW
6. Module: Section 19.3 “SPI Mode” and
Section 19.4 “I
2
C™ Mode”
In Section 19.3 “SPI Mode”, on page 223, and
Section 19.4 “I
2
C™ Mode”, on page 233, the
following new note is included to describe the
procedure to disable the MSSPx module:
7. Module: Figure 19-10: I
2
C™ Slave Mode
Timing (Transmission, 7-Bit
Address)
On page 244, the figure is replaced with the new
timing diagram provided in Figure 19-10.
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
ERASE_ROW
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Row Erase operation
BCF INTCON, GIE ; disable interrupts
Required MOVLW 55h
Sequence MOVWF EECON2 ; write 55h
MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
Note: Disabling the MSSPx module by clearing
the SSPEN (SSPxCON1<5>) bit may not
reset the module. It is recommended to
clear the SSPxSTAT, SSPxCON1 and
SSPxCON2 registers and select the mode
prior to setting the SSPEN bit to enable
the MSSPx module.