Datasheet
Table Of Contents
- TABLE 1: Silicon DEVREV Values
- TABLE 2: Silicon Issue Summary
- Silicon Errata Issues
- Data Sheet Clarifications
- 1. Module: Table 27-1: Memory Programming Requirements
- 2. Module: Table 27-2: Comparator Specifications
- 3. Module: Table 27-4: Internal Voltage Regulator Specifications
- 4. Module: Section 27.3 “DC Characteristics: PIC18F87J11 Family (Industrial)”
- 5. Module: Example 6-2: Erasing a Flash Program Memory Row
- 6. Module: Section 19.3 “SPI Mode” and Section 19.4 “I2C™ Mode”
- 7. Module: Figure 19-10: I2C™ Slave Mode Timing (Transmission, 7-Bit Address)
- 8. Module: Figure 19-24: I2C™ Master Mode Waveform (Reception, 7-Bit Address)
- 9. Module: Table 1-3: PIC18F6XJ1X Pinout I/O Descriptions
- 10. Module: Memory Organization
- 11. Module: Memory Organization
- 12. Module: Electrical Specification
- Document Revision History
- Worldwide Sales and Service

2011 Microchip Technology Inc. DS80495E-page 7
PIC18F87J11 FAMILY
4. Module: Section 27.3 “DC
Characteristics: PIC18F87J11
Family (Industrial)”
On page 396, the characteristics and conditions of the
Input Leakage Current are updated for the Analog
(D060) and included for the Digital (D060A) I/O ports.
The changed values are indicated in bold text in the
following table:
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C T
A +85°C for industrial
Param
No.
Symbol Characteristic Min Max Units Conditions
V
IL Input Low Voltage
All I/O Ports:
D030 with TTL Buffer V
SS 0.15 VDD VVDD < 3.3V
D030A — 0.8 V 3.3V V
DD 3.6V
D031 with Schmitt Trigger Buffer VSS 0.2 VDD V
D032 MCLR
VSS 0.2 VDD V
D033 OSC1 V
SS 0.3 VDD V HS, HSPLL modes
D033A
D034
OSC1
T1CKI
VSS
VSS
0.2 VDD
0.3
V
V
EC, ECPLL modes
VIH Input High Voltage
I/O Ports with Non
5.5V Tolerance:
(2)
D040 with TTL Buffer 0.25 VDD + 0.8V VDD VVDD < 3.3V
D040A 2.0 VDD V3.3V VDD 3.6V
D041 with Schmitt Trigger Buffer 0.8 V
DD VDD V
I/O Ports with
5.5V Tolerance:
(2)
Dxxx with TTL Buffer 0.25 VDD + 0.8V 5.5 V VDD < 3.3V
DxxxA 2.0 5.5 V 3.3V VDD 3.6V
Dxxx with Schmitt Trigger Buffer 0.8 VDD 5.5 V
D042 MCLR
0.8 VDD VDD V
D043 OSC1 0.7 V
DD VDD V HS, HSPLL modes
D043A
D044
OSC1
T1CKI
0.8 VDD
1.6
V
DD
VDD
V
V
EC, ECPLL modes
I
IL Input Leakage Current
(1)
D060 I/O Ports with Non
5.5V Tolerance
(2)
— 1 AVSS VPIN VDD,
Pin at high-impedance
D060A I/O Ports with
5.5V Tolerance
(2)
— 1 AVSS VPIN 5.5V,
Pin at high-impedance
D061 MCLR
— 1 AVss VPIN VDD
D063 OSC1 — 5 AVss VPIN VDD
Note 1: Negative current is defined as current sourced by the pin.
2: Refer to Table 10-1 for the pins that have corresponding tolerance limits.