Datasheet

Table Of Contents
PIC18F87J11 FAMILY
DS80495E-page 4 2011 Microchip Technology Inc.
4. Module: SRAM
Any access to SRAM, either in the form of read
or write operations, will increase the current con-
sumption of the device, depending on how often
the SRAM is accessed. A small current increase
is normal, but in this cited silicon revision, the
difference may be significant and of particular
concern for low-power applications.
For further details, see Table 3.
TABLE 3: TYPICAL CURRENT
CONSUMPTION
Work around
None.
Affected Silicon Revisions
5. Module: Low-Voltage Detect
The LVDSTAT, VDDCORE status bit (WDTCON<6>),
is not implemented in this revision of silicon.
Work around
None.
Affected Silicon Revisions
6. Module: MSSPx (I
2
C™ Master)
If the module is in I
2
C Master mode, and the
slave performs clock stretching, the first clock
pulse after the slave releases the SCLx line may
be narrower than the configured clock width.
This may result in the slave missing the first
clock in the next transmission/reception.
Work around
If the module is in I
2
C Master mode, do not allow
the slave to perform clock stretching. Alter-
nately, the master can slow down the SCLx
clock frequency to a level where the slave can
detect the narrowed clock pulse.
Affected Silicon Revisions
7. Module: Enhanced Universal
Synchronous Asynchronous
Receiver Transmitter (EUSART)
In Synchronous Slave Transmission mode, the
TRMT bit (TXSTA<1>) may not indicate when
the TSR register is empty.
Work around
Instead of polling the TRMT bit to determine the
status of the EUSART, poll the TXIF flag
(PIR1<4>) to determine when new data can be
written to the TXREG register.
Affected Silicon Revisions
Case 1:
Voltage Regulator Enabled
Temperature = +25°C
SEC_RUN mode using 32 kHz Timer1 Crystal
Condition IDD (A) VDD (V)
No RAM access
(1)
59 3.3
Typ RAM access
(2)
201 3.3
Extreme RAM access
(3)
906 3.3
Case 2:
Voltage Regulator Disabled
V
DDCORE is tied to VDD
Temperature = +25°C
SEC_RUN mode using 32 kHz Timer1 Crystal
Condition I
DD (A)
V
DD
(V)
VDDCORE
(V)
No RAM access
(1)
20 2.5 2.5
Typ RAM access
(2)
132 2.5 2.5
Extreme RAM access
(3)
723 2.5 2.5
Note 1: Code execution patterns where no
instructions access SRAM.
2: Code execution that accesses SRAM,
once every seven instruction cycles.
3: Code execution where every instruction
cycle executes an instruction that
accesses SRAM.
A1 A2 A4 A5
A6 C1 C2
X
A1 A2 A4 A5 A6 C1 C2
X
A1 A2 A4 A5 A6 C1 C2
XXXX
XX
A1 A2 A4 A5 A6 C1 C2
XXXX
XXX