Datasheet

PIC18F87J11 FAMILY
DS80495E-page 2  2011 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature
Item
Num
Issue Summary
Affected Revisions
(1)
A1 A2 A4 A5 A6 C1 C2
MSSPx
I
2
C™ Slave
Reception
1.
When configured for I
2
C slave reception, the
MSSPx module may not receive the correct
data if the SSPxBUF register is not read
within a window after an SSPxIF interrupt
occurs.
XXXXXXX
Oscillator
Configuration
PLL 2.
When Phase Lock Loop (PLL) is enabled, if
the PLL input frequency is higher than
8 MHz, there may be problems accessing
the RAM.
XX
Voltage
Regulator
V
DDCORE 3.
If V
DDCORE drops below approximately
2.45V, while the on-chip core voltage regula-
tor is enabled and operating in Voltage
Tracking mode, the REGSLP bit
(WDTCON <7>) will be automatically
cleared.
X
SRAM Read/Write 4.
Any read or write access to SRAM will
increase the current consumption of the
device – varying with how often the SRAM is
accessed.
X
Low-Voltage
Detect
LVDSTAT 5.
The LVDSTAT V
DDCORE status bit is not
implemented in the cited revision of silicon.
X
MSSPx
I
2
C™ Master
mode
6.
In Master mode, the first clock may become
narrower than the configuration width if the
slave performs a clock stretch and release.
XXXXXX
EUSART
Synchronous
Mode
7.
The TRMT bit may not indicate when the
TSR register is empty.
XXXXXXX
Note 1: Only those issues indicated in the last column apply to the current silicon revision.