Datasheet
Table Of Contents
- TABLE 1: Silicon DEVREV Values
- TABLE 2: Silicon Issue Summary
- Silicon Errata Issues
- Data Sheet Clarifications
- 1. Module: Table 27-1: Memory Programming Requirements
- 2. Module: Table 27-2: Comparator Specifications
- 3. Module: Table 27-4: Internal Voltage Regulator Specifications
- 4. Module: Section 27.3 “DC Characteristics: PIC18F87J11 Family (Industrial)”
- 5. Module: Example 6-2: Erasing a Flash Program Memory Row
- 6. Module: Section 19.3 “SPI Mode” and Section 19.4 “I2C™ Mode”
- 7. Module: Figure 19-10: I2C™ Slave Mode Timing (Transmission, 7-Bit Address)
- 8. Module: Figure 19-24: I2C™ Master Mode Waveform (Reception, 7-Bit Address)
- 9. Module: Table 1-3: PIC18F6XJ1X Pinout I/O Descriptions
- 10. Module: Memory Organization
- 11. Module: Memory Organization
- 12. Module: Electrical Specification
- Document Revision History
- Worldwide Sales and Service

2011 Microchip Technology Inc. DS80495E-page 15
PIC18F87J11 FAMILY
12. Module: Electrical Specification
Changes have been made to the VBOR specification,
Parameter Number D005 in Table 27.1, as shown in
bold text in the updated table below.
27.1 DC Characteristics: Supply Voltage
PIC18F87J11 Family (Industrial)
PIC18F87J11 Family
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C T
A +85°C for industrial
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
D001 V
DD Supply Voltage VDDCORE
2.0
—
—
3.6
3.6
V
V
ENVREG tied to V
SS
ENVREG tied to VDD
D001B VDDCORE External Supply for
Microcontroller Core
2.0 — 2.70 V ENVREG tied to VSS
D001C AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V
D001D AVSS Analog Ground Potential VSS – 0.3 — VSS + 0.3 V
D002 VDR RAM Data Retention
Voltage
(1)
1.5 — — V
D003 V
POR VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
— — 0.7 V See Section 5.3 “Power-on
Reset (POR)” for details
D004 SVDD VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.05 — — V/ms See Section 5.3 “Power-on
Reset (POR)” for details
D005 VBOR Brown-out Reset Voltage 1.75
(2)
2.0 2.4 V
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.
2: When the BOR is enabled, the part will continue to operate until the BOR occurs. This is valid,
although V
DD may be below the minimum VDD voltage.