User manual

PICkit™ Serial Analyzer User’s Guide
DS51647A-page 86 © 2007 Microchip Technology Inc.
The script (above) is interpreted as follows. TAG 0x81 instructs the COMM module to
generate an I
2
C ‘Start’ bit on the I
2
C bus. TAG 0x84 indicates 2 bytes will be transmitted
following the start – 0xA8 and 0x01. The first byte is the I
2
C slave address (with
write/read bit Reset) and a data/command byte of 0x01. The COMM module does not
place any significance on the value of the data bytes but merely transmits them ‘blindly’
– as instructed. The next TAG 0x83 instructs the COMM module to issue a Restart bit
on the I
2
C bus. TAG and data bytes - 0x84, 0x01, 0xA9 – will cause 1 byte (0xA9) to
be transmitted. Here again, the COMM module does not interpret the data – the I
2
C
slave will interpret 0xA9 as an address with write/read bit set. TAG 0x89 followed by
data byte 0x01 instructs the COMM module to attempt to read 1 byte from the slave
then issue a NACK on the bus. Finally, an I
2
C ‘Stop’ bit is issued according to tag 0x82.
The resulting I
2
C transaction looks like this on the bus:
[START][A8][01][RESTART][A9][data byte received][STOP]
As the script is executed, a data stream will be developed using TAGs/CDATA
(described in Table 9-19) and returned to the host software via CBUF2.
TABLE 9-19: I
2
CM ‘DATA’ TAG BYTES
TAG/
CDATA
LEN Name Description
0x80 1 I
2
CM_EVENT_START_TX Start bit event
0 CDATA-TAG
0x81 1 I
2
CM_EVENT_STOP_TX Stop bit event
0 CDATA-TAG
0x82 1 I
2
CM_EVENT_RESTART_TX Restart bit event
0 CDATA-TAG
0x83 1 I
2
CM_EVENT_ACK_TX ACK bit event
0 CDATA-TAG
0x84 1 I
2
CM_EVENT_NACK_TX NACK bit event
0 CDATA-TAG
0x85 1 I
2
CM_EVENT_ACK_RX ACK bit event
0 CDATA-TAG
0x86 1 I
2
CM_EVENT_NACK_RX NACK bit event
0 CDATA-TAG
0x87 2 I
2
CM_EVENT_BYTE_TX BYTE transmit
0 CDATA-TAG
1data
0x88 2 I
2
CM_EVENT_BYTE_RX BYTE transmit
0 CDATA-TAG
1data
0x89 2 I
2
CM_EVENT_XACT_ERR transaction error
0 CDATA-TAG
1 error byte
0x8A 2 I
2
CM_EVENT_STATUS_ERR status error
0 CDATA-TAG
1 error byte