Datasheet

© 2007-2012 Microchip Technology Inc. DS70291G-page 79
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
6.0 RESETS
The Reset module combines all reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
•MCLR
: Master Clear Pin Reset
•SWR: RESET Instruction
• WDTO: Watchdog Timer Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Condition Device Reset
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
A simplified block diagram of the Reset module is
shown in Figure 6-1.
Any active source of Reset will make the SYSRST
signal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state and some are unaffected.
All types of device Reset set a corresponding status bit
in the RCON register to indicate the type of Reset (see
Register 6-1).
A POR clears all the bits, except for the POR bit
(RCON<0>), that are set. The user application can set
or clear any bit at any time during the code execution.
The RCON bits only serve as status bits. Setting a
particular Reset status bit in software does not cause a
device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04 and
dsPIC33FJ128MCX02/X04 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Reset”
(DS70192) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: Refer to the specific peripheral section or
Section 3.0 “CPU” in this data sheet for
register Reset states.
Note: The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
MCLR
VDD
Internal
Regulator
BOR
Sleep or Idle
RESET Instruction
WDT
Module
Glitch Filter
Trap Conflict
Illegal Opcode
Uninitialized W Register
SYSRST
VDD Rise
Detect
POR
Configuration Mismatch