Datasheet

© 2007-2012 Microchip Technology Inc. DS70291G-page 103
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
REGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0
FLTA1IF RTCIF DMA5IF
— — QEI1IF PWM1IF —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FLTA1IF: PWM1 Fault A Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 14 RTCIF: Real-Time Clock and Calendar Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13 DMA5IF: DMA Channel 5 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12-11 Unimplemented: Read as ‘0’
bit 10 QEI1IF: QEI1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9 PWM1IF: PWM1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8-0 Unimplemented: Read as ‘0’