Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SOIC 28 16-Bit 40 null I/O number 21

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dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04

Section 11.0 “I/O Ports” Removed Table 11-1 and added reference to pin diagrams for I/O pin

availability and functionality.

Added paragraph on ADPCFG register default values to Section 11.3

“Configuring Analog Port Pins”.

Added Note box regarding PPS functionality with input mapping to

Section 11.6.2.1 “Input Mapping”.

Section 18.0 “Serial Peripheral

Interface (SPI)”

Added Note 2 and 3 to the SPIxCON1 register (see Register 18-2).

Section 20.0 “Universal

Asynchronous Receiver Transmitter

(UART)”

Updated the Notes in the UxMODE register (see Register 20-1).

Updated the UTXINV bit settings in the UxSTA register and added Note 1

(see Register 20-2).

Section 21.0 “Enhanced CAN

(ECAN™) Module”

Changed bit 11 in the ECAN Control Register 1 (CiCTRL1) to Reserved (see

Section 22.0 “10-bit/12-bit Analog-

to-Digital Converter (ADC1)”

Replaced the ADC1 Module Block Diagrams with new diagrams (see

Figure 22-1 and Figure 22-2).

Updated bit values for ADCS<7:0> and added Notes 1 and 2 to the ADC1

Control Register 3 (AD1CON3) (see Register 22-3).

Added Note 2 to the ADC1 Input Scan Select Register Low (AD1CSSL) (see

Added Note 2 to the ADC1 Port Configuration Register Low (AD1PCFGL)

(see Register 22-8).

Section 23.0 “Audio Digital-to-

Analog Converter (DAC)”

Updated the midpoint voltage in the last sentence of the first paragraph.

Updated the voltage swing values in the last sentence of the last paragraph

in Section 23.3 “DAC Output Format”.

Section 24.0 “Comparator Module” Updated the Comparator Voltage Reference Block Diagram

(see Figure 24-2).

Section 25.0 “Real-Time Clock and

Calendar (RTCC)”

Updated the minimum positive adjust value for CAL<7:0> in the RTCC

Calibration and Configuration (RCFGCAL) Register (see Register 25-1).

Section 28.0 “Special Features” Added Note 1 to the Device Configuration Register Map (see Table 28-1).

Updated Note 1 in the dsPIC33F Configuration Bits Description (see

Table 28-2).

TABLE A-2: MAJOR SECTION UPDATES (CONTINUED)

Section Name Update Description