Datasheet

© 2007-2012 Microchip Technology Inc. DS70291G-page 139
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
bit 3 XWCOL3: Channel 3 DMA RAM Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
bit 2 XWCOL2: Channel 2 DMA RAM Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
REGISTER 8-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0 (CONTINUED)