Datasheet
2009-2012 Microchip Technology Inc. DS70594D-page 83
dsPIC33FJXXXMCX06A/X08A/X10A
TABLE 6-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
Reset Type Clock Source SYSRST Delay
System Clock
Delay
FSCM
Delay
See Notes
POR EC, FRC, LPRC T
POR
+ TSTARTUP + TRST ——1, 2, 3
ECPLL, FRCPLL TPOR
+ TSTARTUP + TRST TLOCK TFSCM 1, 2, 3, 5, 6
XT, HS, SOSC T
POR
+ TSTARTUP + TRST TOST TFSCM 1, 2, 3, 4, 6
XTPLL, HSPLL TPOR
+ TSTARTUP + TRST TOST + TLOCK TFSCM 1, 2, 3, 4, 5, 6
BOR EC, FRC, LPRC T
STARTUP + TRST ——3
ECPLL, FRCPLL TSTARTUP + TRST TLOCK TFSCM 3, 5, 6
XT, HS, SOSC T
STARTUP + TRST TOST TFSCM 3, 4, 6
XTPLL, HSPLL TSTARTUP + TRST TOST + TLOCK TFSCM 3, 4, 5, 6
MCLR
Any Clock TRST ——3
WDT Any Clock TRST ——3
Software Any Clock T
RST ——3
Illegal Opcode Any Clock T
RST ——3
Uninitialized W Any Clock TRST ——3
Trap Conflict Any Clock T
RST ——3
Note 1: TPOR = Power-on Reset delay (10 s nominal).
2: TSTARTUP = Conditional POR delay of 20 s nominal (if on-chip regulator is enabled) or 64 ms nominal
Power-up Timer delay (if regulator is disabled). T
STARTUP is also applied to all returns from powered-down
states, including waking from Sleep mode if the regulator is enabled.
3: T
RST = Internal state Reset time (20 s nominal).
4: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
oscillator clock to the system.
5: T
LOCK = PLL lock time (20 s nominal).
6: T
FSCM = Fail-Safe Clock Monitor delay (100 s nominal).