Datasheet

 2009-2012 Microchip Technology Inc. DS70594D-page 185
dsPIC33FJXXXMCX06A/X08A/X10A
REGISTER 16-6: PWMxCON2: PWMx CONTROL REGISTER 2
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — SEVOPS<3:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — IUE OSYNC UDIS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11-8 SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits
1111 = 1:16 postscale
•
•
0001 = 1:2 postscale
0000 = 1:1 postscale
bit 7-3 Unimplemented: Read as ‘0’
bit 2 IUE: Immediate Update Enable bit
1 = Updates to the active PDC registers are immediate
0 = Updates to the active PDC registers are synchronized to the PWM time base
bit 1 OSYNC: Output Override Synchronization bit
1 = Output overrides via the OVDCON register are synchronized to the PWM time base
0 = Output overrides via the OVDCON register occur on next TCY boundary
bit 0 UDIS: PWM Update Disable bit
1 = Updates from Duty Cycle and Period Buffer registers are disabled
0 = Updates from Duty Cycle and Period Buffer registers are enabled