Datasheet

 2009-2012 Microchip Technology Inc. DS70594D-page 179
dsPIC33FJXXXMCX06A/X08A/X10A
16.0 MOTOR CONTROL PWM
MODULE
This module simplifies the task of generating multiple,
synchronized Pulse-Width Modulated (PWM) outputs.
In particular, the following power and motion control
applications are supported by the PWM module:
• 3-Phase AC Induction Motor
• Switched Reluctance (SR) Motor
• Brushless DC (BLDC) Motor
• Uninterruptible Power Supply (UPS)
The PWM module has the following features:
• Eight PWM I/O pins with four duty cycle generators
• Up to 16-bit resolution
• ‘On-the-fly’ PWM frequency changes
• Edge and Center-Aligned Output modes
• Single Pulse Generation mode
• Interrupt support for asymmetrical updates in
Center-Aligned mode
• Output override control for Electrically
Commutative Motor (ECM) operation
• ‘Special Event’ comparator for scheduling other
peripheral events
• Fault pins to optionally drive each of the PWM
output pins to a defined state
• Duty cycle updates are configurable to be
immediate or synchronized to the PWM time base
This module contains four duty cycle generators,
numbered 1 through 4. The module has eight PWM
output pins, numbered PWM1H/PWM1L through
PWM4H/PWM4L. The eight I/O pins are grouped into
high/low numbered pairs, denoted by the suffix H or L,
respectively. For complementary loads, the low PWM
pins are always the complement of the corresponding
high I/O pin.
The PWM module allows several modes of operation
which are beneficial for specific power control
applications.
Note 1: This data sheet summarizes the fea-
tures of the dsPIC33FJXXXMCX06A/
X08A/X10A family of devices. However,
it is not intended to be a comprehen-
sive reference source. To complement
the information in this data sheet, refer
to Section 14. “Motor Control PWM”
(DS70187) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.