Datasheet

 2009-2012 Microchip Technology Inc. DS70594D-page 153
dsPIC33FJXXXMCX06A/X08A/X10A
10.0 POWER-SAVING FEATURES
The dsPIC33FJXXXMCX06A/X08A/X10A devices
provide the ability to manage power consumption by
selectively managing clocking to the CPU and the
peripherals. In general, a lower clock frequency and a
reduction in the number of circuits being clocked
constitutes lower consumed power.
dsPIC33FJXXXMCX06A/X08A/X10A devices can
manage power consumption in four different ways:
• Clock frequency
• Instruction-based Sleep and Idle modes
• Software-controlled Doze mode
• Selective peripheral control in software
Combinations of these methods can be used to
selectively tailor an application’s power consumption
while still maintaining critical application features, such
as timing-sensitive communications.
10.1 Clock Frequency and Clock
Switching
dsPIC33FJXXXMCX06A/X08A/X10A devices allow a
wide range of clock frequencies to be selected under
application control. If the system clock configuration is
not locked, users can choose low-power or
high-precision oscillators by simply changing the
NOSC bits (OSCCON<10:8>). The process of
changing a system clock during operation, as well as
limitations to the process, are discussed in more detail
in Section 9.0 “Oscillator Configuration”.
10.2 Instruction-Based Power-Saving
Modes
dsPIC33FJXXXMCX06A/X08A/X10A devices have
two special power-saving modes that are entered
through the execution of a special PWRSAV instruction.
Sleep mode stops clock operation and halts all code
execution. Idle mode halts the CPU and code
execution, but allows peripheral modules to continue
operation. The assembly syntax of the PWRSAV
instruction is shown in Example 10-1.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to “wake-up”.
10.2.1 SLEEP MODE
Sleep mode has the following features:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption is reduced to a
minimum, provided that no I/O pin is sourcing
current.
• The Fail-Safe Clock Monitor does not operate
during Sleep mode since the system clock source
is disabled.
• The LPRC clock continues to run in Sleep mode if
the WDT is enabled.
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Some device features or peripherals may continue
to operate in Sleep mode. This includes items such
as the input change notification on the I/O ports
and peripherals that use an external clock input.
Any peripheral that requires the system clock
source for its operation is disabled in Sleep mode.
The device will wake-up from Sleep mode on any of the
following events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep, the processor restarts with the
same clock source that was active when Sleep mode
was entered.
EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX
Note 1: This data sheet summarizes the fea-
tures of the dsPIC33FJXXXMCX06A/
X08A/X10A family of devices. How-
ever, it is not intended to be a compre-
hensive reference source. To
complement the information in this data
sheet, refer to Section 9. “Watchdog
Timer and Power-Saving Modes”
(DS70196) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: SLEEP_MODE and IDLE_MODE are con-
stants defined in the assembler include
file for the selected device.
PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode
PWRSAV #IDLE_MODE ; Put the device into IDLE mode