Datasheet

dsPIC33FJXXXMCX06A/X08A/X10A
DS70594D-page 134  2009-2012 Microchip Technology Inc.
FIGURE 8-1: TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS
CPU
SRAM
DMA RAM
CPU Peripheral DS Bus
Peripheral 3
DMA
Peripheral
Non-DMA
SRAM X-Bus
PORT 2PORT 1
Peripheral 1
DMA
Ready
Peripheral 2
DMA
Ready
Ready
Ready
DMA DS Bus
CPU DMA
CPU
DMA
CPU
DMA
Peripheral Indirect Address
Note: For clarity, CPU and DMA address buses are not shown.
DMA
Control
DMA Controller
DMA
Channels