Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 64 (10x10) 16-Bit 40 null I/O number 53

 2009-2012 Microchip Technology Inc. DS70594D-page 1

dsPIC33FJXXXMCX06A/X08A/X10A

Operating Conditions

• 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS

• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS

Core: 16-bit dsPIC33F CPU

• Code-efficient (C and Assembly) architecture

• Two 40-bit wide accumulators

• Single-cycle (MAC/MPY) with dual data fetch

• Single-cycle mixed-sign MUL plus hardware

divide

Clock Management

• ±2% internal oscillator

• Programmable PLLs and oscillator clock sources

• Fail-Safe Clock Monitor (FSCM)

• Independent Watchdog Timer (WDT)

• Fast wake-up and start-up

Power Management

• Low-power management modes (Sleep, Idle,

Doze)

• Integrated Power-on Reset and Brown-out Reset

• 1.35 mA/MHz dynamic current (typical)

•55 μA I

PD current (typical)

Motor Control PWM

• Up to four PWM generators with eight outputs

• Dead Time for rising and falling edges

• 12.5 ns PWM resolution

• PWM support for Motor Control: BLDC, PMSM, ACIM,

and SRM

• Programmable Fault inputs

• Flexible trigger for ADC conversions and configurations

Advanced Analog Features

• Two ADC modules:

- Configurable as 10-bit, 1.1 Msps with four

S&H or 12-bit, 500 ksps with one S&H

- 18 analog inputs on 64-pin devices and up to

32 analog inputs on 100-pin devices

• Flexible and independent ADC trigger sources

Timers/Output Compare/Input Capture

• Up to nine 16-bit timers/counters. Can pair up to

make four 32-bit timers.

• Eight Output Compare modules configurable as

timers/counters

• Eight Input Capture modules

Communication Interfaces

• Two UART modules (10 Mbps)

- With support for LIN 2.0 protocols and IrDA

• Two 4-wire SPI modules (15 Mbps)

• Up to two I

C™ modules (up to 1 Mbaud) with

SMBus support

• Up to two Enhanced CAN (ECAN) modules

(1 Mbaud) with 2.0B support

• Quadrature Encoder Interface (QEI) module

• Data Converter Interface (DCI) module with I

codec support

Input/Output

• Sink/Source up to 10 mA (pin specific) for stan-

dard V

OH/VOL, up to 16 mA (pin specific) for non-

standard V

OH1

• 5V-tolerant pins

• Selectable open drain, pull-ups, and pull-downs

• Up to 5 mA overvoltage clamp current

• External interrupts on all I/O pins

Qualification and Class B Support

• AEC-Q100 REVG (Grade 1 -40ºC to +125ºC)

• AEC-Q100 REVG (Grade 0 -40ºC to +150ºC)

• Class B Safety Library, IEC 60730

Debugger Development Support

• In-circuit and in-application programming

• Two program and two complex data breakpoints

• IEEE 1149.2-compatible (JTAG) boundary scan

• Trace and run-time watch

Packages

Type QFN TQFP TQFP TQFP

Pin Count 64 64 80 100

Contact Lead/Pitch 0.50 0.50 0.50 0.40

I/O Pins 53 53 69 85

Dimensions 9x9x0.9 10x10x1 12x12x1 14x14x1

Note: All dimensions are in millimeters (mm) unless specified.

16-bit Digital Signal Controllers (up to 256 KB Flash and

30 KB SRAM) with Motor Control and Advanced Analog

Summary of content (374 pages)

PAGE 1
dsPIC33FJXXXMCX06A/X08A/X10A 16-bit Digital Signal Controllers (up to 256 KB Flash and 30 KB SRAM) with Motor Control and Advanced Analog Operating Conditions Timers/Output Compare/Input Capture • 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS • 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS • Up to nine 16-bit timers/counters. Can pair up to make four 32-bit timers.
PAGE 2
dsPIC33FJXXXMCX06A/X08A/X10A The device names, pin counts, memory sizes and peripheral availability of each device are listed below. The following pages show their pinout diagrams. dsPIC33F PRODUCT FAMILIES The dsPIC33FJXXXMCX06A/X08A/X10A family of devices supports a variety of motor control applications, such as brushless DC motors, single and 3-phase induction motors and switched reluctance motors.
PAGE 3
dsPIC33FJXXXMCX06A/X08A/X10A Pin Diagrams 64-Pin QFN(1) PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 C1TX/RF1 C1RX/RF0 VDD VCAP OC8/UPDN/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 AN3/INDX/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/VREF-/CN3/RB1 PGED3/AN0/VREF+/C
PAGE 4
dsPIC33FJXXXMCX06A/X08A/X10A Pin Diagrams (Continued) 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 C1TX/RF1 C1RX/RF0 VDD VCAP OC8/UPDN/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ128MC506A dsPIC33FJ256MC506A dsPIC33FJ128MC706A dsPIC33FJ64MC706A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SO
PAGE 5
dsPIC33FJXXXMCX06A/X08A/X10A Pin Diagrams (Continued) = Pins are up to 5V tolerant IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 63 62 61 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 OC7/CN15/RD6 C1TX/RF1 C1RX/RF0 VDD VCAP OC8/CN16/UPDN/RD7 75 74 73 72 71 70 69 68 67 66 65 64 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 RG0 RG1 80 79 78 77 76 PWM3L/RE4 PWM2H/RE3 80-Pin TQFP PWM3H/RE5 1 60 PGEC2/SOSCO/T1CK/CN0/RC14 PWM4L/RE6 2 59 PGED2/SOSCI/CN1/RC13 OC1/RD0 PWM4H/RE7 3 58 AN16/T2CK/T7CK/RC1 4 57 IC4/RD11 AN17/T3CK/
PAGE 6
dsPIC33FJXXXMCX06A/X08A/X10A Pin Diagrams (Continued) = Pins are up to 5V tolerant OC2/RD1 IC5/RD12 OC4/RD3 OC3/RD2 OC8/CN16/UPDN/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 CRX2/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VCAP PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PWM3L/RE4 PWM2H/RE3 80-Pin TQFP PWM3H/RE5 1 60 PGEC2/SOSCO/T1CK/CN0/RC14 PWM4L/RE6 2 59 PGED2/SOSCI/CN1/RC13 OC1/RD0 PWM4H/RE7 3 58 AN16/T2CK/T7CK/RC1 4 57 AN17/T3CK/T
PAGE 7
dsPIC33FJXXXMCX06A/X08A/X10A Pin Diagrams (Continued) 100-Pin TQFP RG15 VDD PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/FLTA/INT1/RE8 AN21/FLTB/INT2/RE9 AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4 AN3/INDX/CN5/RB3 AN2/SS1/CN4/RB2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 VSS 74 73 PGEC2/SOSCO/T1CK/CN0/RC14 72 OC1/RD0 IC4/RD11 71 70 69 68 67 66
PAGE 8
dsPIC33FJXXXMCX06A/X08A/X10A Pin Diagrams (Continued) 100-Pin TQFP RG15 VDD PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/FLTA/INT1/RE8 AN21/FLTB/INT2/RE9 AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4 AN3/INDX/CN5/RB3 AN2/SS1/CN4/RB2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 VSS 73 72 PGED2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 71 70 69
PAGE 9
dsPIC33FJXXXMCX06A/X08A/X10A Pin Diagrams (Continued) 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 RG13 RG12 RG14 PWM1H/RE1 PWM1L/RE0 AN23/CN23/RA7 AN22/CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VCAP OC8/UPDN//CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant RG15 VDD PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/R
PAGE 10
dsPIC33FJXXXMCX06A/X08A/X10A Table of Contents dsPIC33F Product Families ................................................................................................................................................................... 2 1.0 Device Overview ........................................................................................................................................................................ 13 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......
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dsPIC33FJXXXMCX06A/X08A/X10A TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PAGE 12
dsPIC33FJXXXMCX06A/X08A/X10A Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33F/PIC24H Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note: To access the documents listed below, browse to the documentation section of the dsPIC33FJ256MC710A product page on the Microchip web site (www.microchip.
PAGE 13
dsPIC33FJXXXMCX06A/X08A/X10A 1.0 DEVICE OVERVIEW Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/X08A/ X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 1-1: dsPIC33FJXXXMCX06A/X08A/X10A GENERAL BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller 16 8 PORTA 16 16 16 Data Latch Data Latch X RAM Y RAM Address Latch Address Latch DMA RAM 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 23 PORTB DMA 16 16 16 Controller PORTC Address Generator Units Address Latch Program Memory EA MUX Data Latch 24 Instruction Reg Control Signals
PAGE 15
dsPIC33FJXXXMCX06A/X08A/X10A TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Type Buffer Type AN0-AN31 I Analog AVDD P P Positive supply for analog modules. This pin must be connected at all times. AVSS P P Ground reference for analog modules. CLKI CLKO I O CN0-CN23 I ST Input change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. C1RX C1TX C2RX C2TX I O I O ST — ST — ECAN1 bus receive pin. ECAN1 bus transmit pin. ECAN2 bus receive pin.
PAGE 16
dsPIC33FJXXXMCX06A/X08A/X10A TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type RA0-RA7 RA9-RA10 RA12-RA15 I/O I/O I/O ST ST ST PORTA is a bidirectional I/O port. RB0-RB15 I/O ST PORTB is a bidirectional I/O port. RC1-RC4 RC12-RC15 I/O I/O ST ST PORTC is a bidirectional I/O port. Pin Name Description RD0-RD15 I/O ST PORTD is a bidirectional I/O port. RE0-RE9 I/O ST PORTE is a bidirectional I/O port. RF0-RF8 RF12-RF13 I/O ST PORTF is a bidirectional I/O port.
PAGE 17
dsPIC33FJXXXMCX06A/X08A/X10A TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type VSS P — VREF+ I Analog Analog voltage reference (high) input. VREF- I Analog Analog voltage reference (low) input. Pin Name Description Ground reference for logic and I/O pins. Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels  2009-2012 Microchip Technology Inc.
PAGE 18
dsPIC33FJXXXMCX06A/X08A/X10A NOTES: DS70594D-page 18  2009-2012 Microchip Technology Inc.
PAGE 19
dsPIC33FJXXXMCX06A/X08A/X10A 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/X08A/ X10A family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
PAGE 20
dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic 10 µF Tantalum R R1 VSS VDD 2.4 VCAP VDD • Device Reset • Device Programming and Debugging C dsPIC33F VSS VDD VSS VDD AVSS VDD AVDD VSS 0.1 µF Ceramic 0.1 µF Ceramic 0.1 µF Ceramic L1(1) Note 1: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and AVDD to improve ADC noise rejection.
PAGE 21
dsPIC33FJXXXMCX06A/X08A/X10A 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.
PAGE 22
dsPIC33FJXXXMCX06A/X08A/X10A 2.7 Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to  8 MHz for start-up with PLL enabled to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start-up in the FRC mode first.
PAGE 23
dsPIC33FJXXXMCX06A/X08A/X10A 3.0 CPU Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/X08A/ X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS70204) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
PAGE 24
dsPIC33FJXXXMCX06A/X08A/X10A 3.3 The dsPIC33FJXXXMCX06A/X08A/X10A devices support 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without a loss of data.
PAGE 25
dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 3-2: dsPIC33FJXXXMCX06A/X08A/X10A PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.
PAGE 26
dsPIC33FJXXXMCX06A/X08A/X10A 3.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2) 111 = CPU interrupt priority level is 7 (15), user interrupts disabled 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 — bit 15 U-0 — R/W-0 SATA bit 7 R/W-0 SATB bit 11 bit 10-8 R/W-0 US R/W-0 EDT(1) R-0 R-0 DL<2:0> R-0 bit 8 Legend: R = Readable bit 0’ = Bit is cleared bit 15-13 bit 12 U-0 — R/W-1 SATDW R/W-0 ACCSAT C = Clearable bit W = Writable bit ‘x = Bit is unknown R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ Unimplemented: Read as ‘0’ US: DSP Mul
PAGE 29
dsPIC33FJXXXMCX06A/X08A/X10A 3.5 Arithmetic Logic Unit (ALU) 3.6 DSP Engine The dsPIC33FJXXXMCX06A/X08A/X10A ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 S a 40 Round t 16 u Logic r a t e 40-Bit Accumulator A 40-Bit Accumulator B Carry/Borrow Out Carry/Borrow In Saturate Adder Negate 40 40 40 16 X Data Bus Barrel Shifter 40 Y Data Bus Sign-Extend 32 Zero Backfill 16 32 33 17-Bit Multiplier/Scaler 16 16 To/From W Array DS70594D-page 30  2009-2012 Microchip Technology Inc.
PAGE 31
dsPIC33FJXXXMCX06A/X08A/X10A 3.6.1 MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17-bit x 17-bit multiplier/scaler is a 33-bit value which is sign-extended to 40 bits.
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dsPIC33FJXXXMCX06A/X08A/X10A The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow, and thus, indicate that a catastrophic overflow has occurred.
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dsPIC33FJXXXMCX06A/X08A/X10A 3.6.2.4 Data Space Write Saturation 3.6.3 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data space can also be saturated – but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder.
PAGE 34
dsPIC33FJXXXMCX06A/X08A/X10A NOTES: DS70594D-page 34  2009-2012 Microchip Technology Inc.
PAGE 35
dsPIC33FJXXXMCX06A/X08A/X10A 4.0 MEMORY ORGANIZATION 4.1 Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/ X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 3. “Data Memory” (DS70202) and Section 4. “Program Memory” (DS70203) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
PAGE 36
dsPIC33FJXXXMCX06A/X08A/X10A 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 All dsPIC33FJXXXMCX06A/X08A/X10A devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 0x000000, with the actual address for the start of code at 0x000002.
PAGE 37
dsPIC33FJXXXMCX06A/X08A/X10A 4.2 Data Address Space The dsPIC33FJXXXMCX06A/X08A/X10A CPU has a separate 16-bit wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. Data memory maps of devices with different RAM sizes are shown in Figure 4-3 through Figure 4-5. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space.
PAGE 38
dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJXXXMCX06A/X08A/X10A DEVICES WITH 8-Kbyte RAM MSb Address MSb 2-Kbyte SFR Space LSb Address 16 Bits LSb 0x0000 0x0001 SFR Space 0x07FE 0x0800 0x07FF 0x0801 8-Kbyte Near Data Space X Data RAM (X) 8-Kbyte SRAM Space 0x17FF 0x1801 0x1FFF 0x2001 0x27FF 0x2801 0x17FE 0x1800 Y Data RAM (Y) 0x1FFE 0x2000 DMA RAM 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70594D-page 38 0x27FE 0x2800 0
PAGE 39
dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 4-4: DATA MEMORY MAP FOR dsPIC33FJXXXMCX06A/X08A/X10A DEVICES WITH 16-Kbyte RAM MSb Address 16 Bits MSb 2-Kbyte SFR Space LSb 0x0000 0x0001 SFR Space 0x07FF 0x0801 0x1FFF 16-Kbyte SRAM Space LSb Address X Data RAM (X) 0x27FF 0x2801 0x3FFF 0x4001 0x47FF 0x4801 0x07FE 0x0800 8-Kbyte Near Data Space 0x1FFE 0x27FE 0x2800 Y Data RAM (Y) 0x3FFE 0x4000 DMA RAM 0x8001 0x47FE 0x4800 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF  2
PAGE 40
dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 4-5: DATA MEMORY MAP FOR dsPIC33FJXXXMCX06A/X08A/X10A DEVICES WITH 30-Kbyte RAM MSb Address MSb 2-Kbyte SFR Space 0x0001 LSb Address 16 Bits LSb 0x0000 SFR Space 0x07FE 0x0800 0x07FF 0x0801 8-Kbyte Near Data Space X Data RAM (X) 30-Kbyte SRAM Space 0x47FF 0x4801 0x47FE 0x4800 Y Data RAM (Y) 0x77FF 0x7800 0x7FFF 0x8001 Optionally Mapped into Program Memory X Data Unimplemented (X) 0xFFFF DS70594D-page 40 DMA RAM 0x77FE 0x7800 0x7FFE 0x8000 0xFFFE  200
PAGE 41
dsPIC33FJXXXMCX06A/X08A/X10A 4.2.5 X AND Y DATA SPACES The core has two data spaces: X and Y. These data spaces can be considered either separate (for some DSP instructions) or as one unified, linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths.
PAGE 42
CPU CORE REGISTERS MAP  2009-2012 Microchip Technology Inc.
PAGE 43
CPU CORE REGISTERS MAP (CONTINUED) SFR Name SFR Addr YMODSRT 004C YMODEND 004E XBREV 0050 BREN DISICNT 0052 — — BSRAM 0750 — — — — — — — — — — — — — IW_BSR IR_BSR RL_BSR 0000 0752 — — — — — — — — — — — — — IW_SSR IR_SSR RL_SSR 0000 SSRAM Legend: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 0 All Resets YS<15:1> 0 xxxx YE<15:1> 1 xxxx Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 XB<14:0> xxxx Disable Interrupts Counter Reg
PAGE 44
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXXMCX10A DEVICES SFR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 CNEN2 0062 — — — — — — — — CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN1
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SFR Name SFR Addr INTERRUPT CONTROLLER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE INTCON2 0082 ALTIVT DISI — — — IFS0 0084 — DMA1IF AD1IF U1TXIF U1RXIF IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF Bit 5 Bit 4 Bit 3 OSCFAIL — 0000 INT1EP INT0EP 0000 OC1IF IC1IF INT0IF 0000 — MI2C1IF SI2C1IF 0000 OVBTE COVTE — — — — — INT4EP INT3EP INT2EP T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC3
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SFR Name SFR Addr TIMER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 TMR1 0100 Timer1 Register PR1 0102 Period Register 1 T1CON 0104 TMR2 0106 TON — TSIDL — — — TMR3HLD 0108 — — — Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 FFFF TGATE TCKPS<1:0> — TSYNC TCS — 0000 Timer2 Register 0000 Timer3 Holding Register (for 32-bit timer operations only) xxxx TMR3 010A Timer3 Register 0000 PR2 010C Period Register 2 FFFF
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SFR Name SFR Addr IC1BUF 0140 IC1CON 0142 IC2BUF 0144 IC2CON 0146 IC3BUF 0148 IC3CON 014A IC4BUF 014C IC4CON 014E IC5BUF 0150 IC5CON 0152 IC6BUF 0154 IC6CON 0156 IC7BUF 0158 IC7CON 015A IC8BUF 015C IC8CON 015E Legend: INPUT CAPTURE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 — — ICSIDL — — — — — — ICSIDL — — — — Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ICI<1:0> ICOV ICBNE ICM<2:0> ICI<1:0> ICOV ICBNE ICM<2:0> ICI
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SFR Name OUTPUT COMPARE REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 OC1RS 0180 Output Compare 1 Secondary Register OC1R 0182 Output Compare 1 Register OC1CON 0184 OC2RS 0186 Output Compare 2 Secondary Register OC2R 0188 Output Compare 2 Register OC2CON 018A OC3RS 018C Output Compare 3 Secondary Register OC3R 018E Output Compare 3 Register OC3CON 0190 OC4RS 0192 Output Compare 4 Secondary Register OC4R 0194 Output Compare 4
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SFR Name Addr.
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SFR Name Addr .
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SFR Name SFR Addr UART1 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 — USIDL IREN RTSMD — — UTXBRK UTXEN Bit 9 Bit 8 Bit 7 Bit 6 UEN1 UEN0 WAKE LPBACK UTXBF TRMT Bit 5 Bit 4 Bit 3 ABAUD URXINV BRGH ADDEN RIDLE PERR U1MODE 0220 UARTEN U1STA 0222 UTXISEL1 U1TXREG 0224 — — — — — — — UART1 Transmit Register U1RXREG 0226 — — — — — — — UART1 Receive Register U1BRG 0228 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’.
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File Name Addr ADC1BUF0 0300 AD1CON1 0320 AD1CON2 0322 ADC1 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 ADON — ADSIDL ADDMABM — AD12B FORM<1:0> — — CSCNA CHPS<1:0> — — Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 — SIMSAM ASAM SAMP DONE 0000 BUFM ALTS 0000 CH123SA 0000 ADC1 Data Buffer 0 VCFG<2:0> AD1CON3 0324 ADRC — — AD1CHS123 0326 — — — AD1CHS0 0328 CH0NB — — xxxx SSRC<2:0> BUFS — CH123SB — — SMPI<3:0> SAMC<4:0> ADC
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File Name Addr DMA REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 DMA0CON 0380 CHEN SIZE DIR HALF NULLW — — — — — DMA0REQ 0382 FORCE — — — — — — — — Bit 5 Bit 4 AMODE<1:0> Bit 3 Bit 2 — — Bit 1 Bit 0 MODE<1:0> IRQSEL<6:0> All Resets 0000 0000 DMA0STA 0384 STA<15:0> 0000 DMA0STB 0386 STB<15:0> 0000 DMA0PAD 0388 PAD<15:0> DMA0CNT 038A — — — — — — DMA1CON 038C CHEN SIZE DIR HALF NULLW — — — — DMA1REQ 038E
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File Name Addr DMA REGISTER MAP (CONTINUED) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 DMA5CNT 03C6 — — — — — — DMA6CON 03C8 CHEN SIZE DIR HALF NULLW — — — — — — — — — — — — DMA5PAD Bit 9 Bit 8 03C4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PAD<15:0> DMA6REQ 03CA FORCE All Resets 0000 CNT<9:0> — AMODE<1:0> 0000 — — MODE<1:0> IRQSEL<6:0> 0000 0000 DMA6STA 03CC STA<15:0> 0000 DMA6STB 03CE STB<15:0> 0000 DMA6PAD 03D0 PAD<15:0> DMA6CNT 03D2
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File Name ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 0 OR 1 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 C1CTRL1 0400 — — CSIDL ABAT — C1CTRL2 0402 — — — — — C1VEC 0404 — — — C1FCTRL 0406 — — C1FIFO 0408 — — DMABS<2:0> Bit 10 Bit 9 Bit 8 Bit 7 — — — — — REQOP<2:0> — Bit 5 OPMODE<2:0> FILHIT<4:0> — Bit 6 — — — — — — — Bit 4 Bit 3 — CANCAP Bit 1 Bit 0 — — WIN DNCNT<4:0> — FBP<5:0> Bit 2 All Resets 0480 0000 ICODE<6:0> 0000 FSA<4:0> 0000 FNRB
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File Name ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 1 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 0400041E Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets See definition when WIN = x  2009-2012 Microchip Technology Inc.
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File Name ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 1 (CONTINUED) Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 C1RXF11SID 046C SID<10:3> C1RXF11EID 046E EID<15:8> C1RXF12SID 0470 SID<10:3> C1RXF12EID 0472 EID<15:8> C1RXF13SID 0474 SID<10:3> C1RXF13EID 0476 EID<15:8> C1RXF14SID 0478 SID<10:3> C1RXF14EID 047A EID<15:8> C1RXF15SID 047C SID<10:3> C1RXF15EID 047E EID<15:8> Legend: Bit 10 Bit 9 Bit 8 Bit 7 x = unknown value on Reset, — = unimplemented, read as ‘0’.
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File Name ECAN2 REGISTER MAP WHEN WIN (C1CTRL<0>) = 0 OR 1 FOR dsPIC33FJXXXMC708A/710A DEVICES Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 C2CTRL1 0500 — — CSIDL ABAT — C2CTRL2 0502 — — — — — C2VEC 0504 — — — C2FCTRL 0506 — — TXBP RXBP TXWAR — — — Bit 8 Bit 7 — — — — — REQOP<2:0> — Bit 5 OPMODE<2:0> FILHIT<4:0> DMABS<2:0> Bit 6 — — — — Bit 4 Bit 3 — CANCAP Bit 1 Bit 0 — — WIN DNCNT<4:0> — — Bit 2 0480 0000 ICODE<6:0> — All Rese
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File Name Addr ECAN2 REGISTER MAP WHEN WIN (C1CTRL<0>) = 1 FOR dsPIC33FJXXXMC708A/710A DEVICES Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 0500051E Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets See definition when WIN = x DS70594D-page 59 C2BUFPNT1 0520 F3BP<3:0> F2BP<3:0> F1BP<3:0> F0BP<3:0> 0000 C2BUFPNT2 0522 F7BP<3:0> F6BP<3:0> F5BP<3:0> F4BP<3:0> 0000 C2BUFPNT3 0524 F11BP<3:0> F10BP<3:0> F9BP<3:0> F8BP<3:0> 0000 C2BUFPNT4 0526 F15BP<3:
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File Name Addr ECAN2 REGISTER MAP WHEN WIN (C1CTRL<0>) = 1 FOR dsPIC33FJXXXMC708A/710A DEVICES (CONTINUED) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 C2RXF11SID 056C SID<10:3> C2RXF11EID 056E EID<15:8> C2RXF12SID 0570 SID<10:3> C2RXF12EID 0572 EID<15:8> C2RXF13SID 0574 SID<10:3> C2RXF13EID 0576 EID<15:8> C2RXF14SID 0578 SID<10:3> C2RXF14EID 057A EID<15:8> C2RXF15SID 057C SID<10:3> C2RXF15EID 057E EID<15:8> Legend: Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 SID<2:0> Bit 4 Bit 3
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PORTC REGISTER MAP(1) Bit 13 Bit 12 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — — — — — — TRISC4 TRISC3 TRISC2 TRISC1 — F01E — — — — — — — RC4 RC3 RC2 RC1 — xxxx — — — — — — — LATC4 LATC3 LATC2 LATC1 — xxxx TRISC 02CC PORTC 02CE RC15 RC14 RC13 RC12 LATC 02D0 LATC15 LATC14 LATC13 LATC12 Legend: Note 1: x = unknown value on Reset, — = unimplemented, read as ‘0’.
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PORTG REGISTER MAP(1) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISG 02E4 TRISG15 TRISG14 TRISG13 TRISG12 — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1 TRISG0 F3CF PORTG 02E6 RG15 RG14 RG13 RG12 — — RG9 RG8 RG7 RG6 — — RG3 RG2 RG1 RG0 xxxx LATG 02E8 LATG15 LATG14 LATG13 LATG12 — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 LATG1 LATG0 xxxx
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dsPIC33FJXXXMCX06A/X08A/X10A 4.2.7 4.2.8 SOFTWARE STACK In addition to its use as a working register, the W15 register in the dsPIC33FJXXXMCX06A/X08A/X10A devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 4-6.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 4-36: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the EA. Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value.
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dsPIC33FJXXXMCX06A/X08A/X10A Modulo Addressing can operate in either data or program space (since the Data Pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into program space) and Y data spaces. Modulo Addressing can operate on any W register pointer. However, it is not advisable to use W14 or W15 for Modulo Addressing, since these two registers are used as the Stack Frame Pointer and Stack Pointer, respectively.
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dsPIC33FJXXXMCX06A/X08A/X10A 4.4.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. It is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes may, therefore, jump beyond boundaries and still be adjusted correctly. Note: 4.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 4-8: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-37: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0
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dsPIC33FJXXXMCX06A/X08A/X10A 4.6 4.6.1 Interfacing Program and Data Memory Spaces Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. The dsPIC33FJXXXMCX06A/X08A/X10A architecture uses a 24-bit wide program space and a 16-bit wide data space.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) Program Counter 0 0 23 bits EA Table Operations(2) 1/0 1/0 TBLPAG 8 bits 16 bits 24 bits Select Program Space Visibility(1) (Remapping) 0 EA 1 0 PSVPAG 8 bits 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces.
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dsPIC33FJXXXMCX06A/X08A/X10A 4.6.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS 2. The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word.
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dsPIC33FJXXXMCX06A/X08A/X10A 4.6.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H).
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dsPIC33FJXXXMCX06A/X08A/X10A NOTES: DS70594D-page 72  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A 5.0 three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. FLASH PROGRAM MEMORY Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/X08A/ X10A family of devices.
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dsPIC33FJXXXMCX06A/X08A/X10A 5.2 RTSP Operation The dsPIC33FJXXXMCX06A/X08A/X10A Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase a page of memory at a time, which consists of eight rows (512 instructions), and to program one row or one word at a time. Table 26-12 shows typical erase and programming times.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 5-1: R/SO-0(1) NVMCON: FLASH MEMORY CONTROL REGISTER R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WREN WRERR — — — — — WR bit 15 bit 8 R/W-0(1) U-0 — U-0 ERASE — U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) NVMOP<3:0>(2) — bit 7 bit 0 Legend: R = Readable bit SO = Settable Only bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3-0 x
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dsPIC33FJXXXMCX06A/X08A/X10A 5.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. The user can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is as follows: 1. 2. 3. Read eight rows of program memory (512 instructions) and store it in data RAM. Update the program data in RAM with the desired new data.
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dsPIC33FJXXXMCX06A/X08A/X10A EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BY
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dsPIC33FJXXXMCX06A/X08A/X10A NOTES: DS70594D-page 78  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A 6.0 A simplified block diagram of the Reset module is shown in Figure 6-1. RESET Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/ X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Reset” (DS70192) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
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dsPIC33FJXXXMCX06A/X08A/X10A RCON: RESET CONTROL REGISTER(1) REGISTER 6-1: R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 TRAPR IOPUWR — — — — — VREGS(3) bit 15 bit 8 R/W-0 R/W-0 EXTR SWR R/W-0 (2) SWDTEN R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Note 1: 2: 3: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 6-1: RESET FLAG BIT OPERATION Flag Bit Setting Event Clearing Event TRAPR (RCON<15>) Trap conflict event POR, BOR IOPUWR (RCON<14>) Illegal opcode or uninitialized W register access POR, BOR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET instruction POR, BOR WDTO (RCON<4>) WDT time-out PWRSAV instruction, POR, BOR SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR, BOR IDLE (RCON<2>) PWRSAV #IDLE instruction POR, BOR BOR (RCON<1>) BOR, POR — POR (
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 6-3: Reset Type POR BOR RESET DELAY TIMES FOR VARIOUS DEVICE RESETS SYSRST Delay System Clock Delay FSCM Delay EC, FRC, LPRC TPOR + TSTARTUP + TRST — — Clock Source See Notes 1, 2, 3 ECPLL, FRCPLL TPOR + TSTARTUP + TRST TLOCK TFSCM 1, 2, 3, 5, 6 XT, HS, SOSC TPOR + TSTARTUP + TRST TOST TFSCM 1, 2, 3, 4, 6 XTPLL, HSPLL TPOR + TSTARTUP + TRST TOST + TLOCK TFSCM 1, 2, 3, 4, 5, 6 EC, FRC, LPRC TSTARTUP + TRST — — ECPLL, FRCPLL TSTARTUP + TRST TL
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dsPIC33FJXXXMCX06A/X08A/X10A 6.2.1 POR AND LONG OSCILLATOR START-UP TIMES The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: • The oscillator circuit has not begun to oscillate.
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dsPIC33FJXXXMCX06A/X08A/X10A 7.0 INTERRUPT CONTROLLER Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/ X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 6. “Interrupts” (DS70184) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
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dsPIC33FJXXXMCX06A/X08A/X10A Decreasing Natural Order Priority FIGURE 7-1: Note 1: DS70594D-page 86 dsPIC33FJXXXMCX06A/X08A/X10A INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 Reserve
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 7-1: INTERRUPT VECTORS Vector Number Interrupt Request (IRQ) Number IVT Address AIVT Address 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 0x000014 0x000016 0x000018 0x00001A 0x00001C 0x00001E 0x000020 0x000022 0x000024 0x000026 0x000028 0x00002A 0x00
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 7-1: INTERRUPT VECTORS (CONTINUED) Vector Number Interrupt Request (IRQ) Number IVT Address AIVT Address 54 55 56 57 58 59 60 61 62 63 64 65 66 69 70 46 47 48 49 50 51 52 53 54 55 56 57 58 61 62 0x000070 0x000072 0x000074 0x000076 0x000078 0x00007A 0x00007C 0x00007E 0x000080 0x000082 0x000084 0x000086 0x000088 0x00008E 0x000090 0x000170 0x000172 0x000174 0x000176 0x000178 0x00017A 0x00017C 0x00017E 0x000180 0x000182 0x000184 0x000186 0x000188 0x00018E 0x000190 In
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dsPIC33FJXXXMCX06A/X08A/X10A 7.3 Interrupt Control and Status Registers dsPIC33FJXXXMCX06A/X08A/X10A devices implement a total of 30 registers for the interrupt controller: • • • • • • INTCON1 INTCON2 IFS0 through IFS4 IEC0 through IEC4 IPC0 through IPC17 INTTREG Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable bit (NSTDIS) as well as the control and status flags for the processor trap sources.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-1: SR: CPU STATUS REGISTER(1) R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R-0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0(3) IPL2 (2) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL1(2) IPL0(2) RA N OV Z C bit 7 bit 0 Legend: C = Clearable bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Settable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown IPL<2:0>: CPU Interrupt P
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interr
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS705
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use Alternate Interrupt
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF DMA01IF T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplem
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2009-201
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA21IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 IC8IF IC7IF AD2IF INT1IF CNIF — MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 U2TXIF:
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED) bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 Unimplemented: Read as ‘0’ bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interr
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T6IF DMA4IF — OC8IF OC7IF OC6IF OC5IF IC6IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 T6IF: Time
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 (CONTINUED) bit 2 C1RXIF: ECAN1 Receive Data Ready Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2009-2012 Microchi
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 FLTAIF — DMA5IF — — QEIIF PWMIF C2IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTAIF: PWM Fault A I
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 (CONTINUED) bit 1 SI2C2IF: I2C2 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 T7IF: Timer7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C2TXIF C1TXIF DMA7IF DMA6IF — U2EIF U1EIF FLTBIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 C2TXIF: ECAN2 Transm
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70594D-page 104  2009-2012 Microchip Technology
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 IC8IE IC7IE AD2IE INT1IE CNIE — MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 U2TXIE: UART2 Transmitte
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 Unimplemented: Read as ‘0’ bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70594D-pa
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T6IE DMA4IE — OC8IE OC7IE OC6IE OC5IE IC6IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 T6IE: Timer6 Interrupt Ena
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 (CONTINUED) bit 2 C1RXIE: ECAN1 Receive Data Ready Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70594D-page 108  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 FLTAIE — DMA5IE — — QEIIE PWMIE C2IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 FLTAIE: PWM Fault A Interrupt Enable
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 (CONTINUED) bit 1 SI2C2IE: I2C2 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 T7IE: Timer7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70594D-page 110  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C2TXIE C1TXIE DMA7IE DMA6IE — U2EIE U1EIE FLTBIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 C2TXIE: ECAN2 Transmit Data Request
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-15: U-0 IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 R/W-1 — R/W-0 R/W-0 T1IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC1IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 INT0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-16: U-0 IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 R/W-1 — R/W-0 R/W-0 T2IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC2IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC2IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 DMA0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrup
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-17: U-0 IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 R/W-1 — R/W-0 R/W-0 U1RXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 SPI1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 SPI1EIP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 T3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priori
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 DMA1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 AD1IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 U1TXIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 DMA1IP<2:0>: DMA Channel 1 Da
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-19: U-0 IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 R/W-1 — R/W-0 R/W-0 CNIP<2:0> U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 MI2C1IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 SI2C1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bit
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-20: U-0 IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 R/W-1 — R/W-0 R/W-0 IC8IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 IC7IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 AD2IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 INT1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP<2:0>: Input Capture Channel 8 Interrupt
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-21: U-0 IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 R/W-1 — R/W-0 R/W-0 T4IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC4IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 OC3IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 DMA2IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interrup
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-22: U-0 IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 R/W-1 — R/W-0 R/W-0 U2TXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 U2RXIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 INT2IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 T5IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Prio
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-23: U-0 IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 R/W-1 — R/W-0 R/W-0 C1IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 C1RXIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 SPI2IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 SPI2EIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 C1IP<2:0>: ECAN1 Event Interrupt Priority b
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-24: U-0 IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 R/W-1 — R/W-0 R/W-0 IC5IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 IC4IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC3IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 DMA3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC5IP<2:0>: Input Capture
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-25: U-0 IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 R/W-1 — R/W-0 R/W-0 OC7IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC6IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 OC5IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 IC6IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 OC7IP<2:0>: Output Compare Channel 7 Interru
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-26: U-0 IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 R/W-1 — R/W-0 R/W-0 T6IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 DMA4IP<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 OC8IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T6IP<2:0>: Timer6 Interrupt Prio
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-27: U-0 IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 R/W-1 — R/W-0 R/W-0 T8IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 MI2C2IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 SI2C2IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 T7IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T8IP<2:0>: Timer8 Interrupt Priority bits 1
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-28: U-0 IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 R/W-1 — R/W-0 R/W-0 C2RXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 INT4IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 INT3IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 T9IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 C2RXIP<2:0>: ECAN2 Receive Data Ready Inte
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-29: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 U-1 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 QEIIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 PWMIP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 C2IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 QEIIP<2:0>: QEI Interrupt Priority bits 111 = Inter
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-30: U-0 IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 R/W-1 — R/W-0 R/W-0 FLTAIP<2:0> U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 DMA5IP<2:0> R/W-0 U-0 U-1 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 FLTAIP<2:0>: PWM Fault A Interrupt Prior
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-31: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 U2EIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 U1EIP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 FLTBIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 U2EIP<2:0>: UART2 Error Interrupt Priority bits 1
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-32: U-0 IPC17: INTERRUPT PRIORITY CONTROL REGISTER 17 R/W-1 — R/W-0 R/W-0 C2TXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 C1TXIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 DMA7IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 DMA6IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 C2TXIP<2:0>: ECAN2 T
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 7-33: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 — — — — R-0 R-0 R-0 R-0 ILR<3:0> bit 15 bit 8 U-0 R-0 R-0 — R-0 R-0 R-0 R-0 R-0 VECNUM<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU interrupt priority level
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dsPIC33FJXXXMCX06A/X08A/X10A 7.4 Interrupt Setup Procedures 7.4.1 INITIALIZATION To configure an interrupt source, do the following: 1. 2. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source.
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dsPIC33FJXXXMCX06A/X08A/X10A 8.0 DIRECT MEMORY ACCESS (DMA) Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 22. “Direct Memory Access (DMA)” (DS70182) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 8-1: TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS Peripheral Indirect Address DMA Control DMA Controller DMA RAM SRAM DMA Ready Peripheral 3 DMA Channels PORT 1 PORT 2 SRAM X-Bus CPU DMA DMA DS Bus CPU Peripheral DS Bus CPU Non-DMA Ready Peripheral CPU DMA DMA Ready Peripheral 1 CPU DMA DMA Ready Peripheral 2 Note: For clarity, CPU and DMA address buses are not shown. DS70594D-page 134  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A 8.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 8-2: DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 FORCE(1) — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 — IRQSEL6(2) IRQSEL5(2) R/W-0 U-0 IRQSEL4(2) IRQSEL3(2) U-0 R/W-0 R/W-0 IRQSEL2(2) IRQSEL1(2) IRQSEL0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FORCE: Force DMA Tr
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 8-3: R/W-0 DMAxSTA: DMA CHANNEL x RAM START ADDRESS OFFSET REGISTER A R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown STA<15:0>: Primary DMA RAM Start Address bits (source or destination) REGISTER 8
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 8-5: R/W-0 DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: x = Bit is unknown PAD<15:0>: Peripheral Address Register bits If the channel is enabled (i.e.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 8-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 XWCOL7 XWCOL6 XWCOL5 XWCOL4 XWCOL3 XWCOL2 XWCOL1 XWCOL0 bit 7 bit 0 C = Clearable bit Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 8-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0 (CONTINUED) bit 3 XWCOL3: Channel 3 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 2 XWCOL2: Channel 2 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 8-8: DMACS1: DMA CONTROLLER STATUS REGISTER 1 U-0 U-0 U-0 U-0 — — — — R-1 R-1 R-1 R-1 LSTCH<3:0> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 LSTCH<3:0>: Last DMA Channel Active bits 1111 = N
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 8-9: R-0 DSADR: MOST RECENT DMA RAM ADDRESS R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<15:8> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits DS70594D-page 142  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A 9.0 The dsPIC33FJXXXMCX06A/X08A/X10A oscillator system provides the following: OSCILLATOR CONFIGURATION Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/ X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. “Oscillator” (DS70186) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.
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dsPIC33FJXXXMCX06A/X08A/X10A 9.1 CPU Clocking System There are seven system clock options provided by the dsPIC33FJXXXMCX06A/X08A/X10A: • • • • • • • FRC Oscillator FRC Oscillator with PLL Primary (XT, HS or EC) Oscillator Primary Oscillator with PLL Secondary (LP) Oscillator LPRC Oscillator FRC Oscillator with Postscaler 9.1.1 SYSTEM CLOCK SOURCES The FRC (Fast RC) internal oscillator runs at a nominal frequency of 7.37 MHz. The user software can tune the FRC frequency.
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dsPIC33FJXXXMCX06A/X08A/X10A For example, suppose a 10 MHz crystal is being used with “XT with PLL” as the selected oscillator mode. If PLLPRE<4:0> = 0, then N1 = 2. This yields a VCO input of 10/2 = 5 MHz, which is within the acceptable range of 0.8-8 MHz. If PLLDIV<8:0> = 0x1E, then M = 32. This yields a VCO output of 5 * 32 = 160 MHz, which is within the 100-200 MHz ranged needed.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 9-1: U-0 OSCCON: OSCILLATOR CONTROL REGISTER(1,3) R-0 — R-0 R-0 COSC<2:0> U-0 R/W-y R/W-y R/W-y NOSC<2:0>(2) — bit 15 bit 8 R/W-0 U-0 R-0 U-0 R/C-0 U-0 R/W-0 R/W-0 CLKLOCK — LOCK — CF — LPOSCEN OSWEN bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: R
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,3) (CONTINUED) bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: 2: 3: Writes to this register require an unlock sequence. Refer to Section 7.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 9-2: R/W-0 CLKDIV: CLOCK DIVISOR REGISTER(2) R/W-0 ROI bit 15 R/W-1 R/W-1 R/W-0 R/W-0 DOZEN(1) DOZE<2:0> R/W-0 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-1 PLLPOST<1:0> U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PLLPRE<4:0> bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Inte
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 9-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PLLDIV<8> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also deno
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 9-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER(2) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TUN<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 = Center frequency + 11.
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dsPIC33FJXXXMCX06A/X08A/X10A 9.2 Clock Switching Operation Applications are free to switch between any of the four clock sources (Primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects that could result from this flexibility, dsPIC33FJXXXMCX06A/X08A/X10A devices have a safeguard lock built into the switch process. Note: 9.2.1 Primary Oscillator mode has three different submodes (XT, HS and EC) which are determined by the POSCMD<1:0> Configuration bits.
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dsPIC33FJXXXMCX06A/X08A/X10A 10.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/ X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
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dsPIC33FJXXXMCX06A/X08A/X10A 10.2.2 IDLE MODE Idle mode has the following features: • The CPU stops executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 10.4 “Peripheral Module Disable”). • If the WDT or FSCM is enabled, the LPRC also remains active.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 I2C1MD U2MD U1MD SPI2MD SPI1MD C2MD C1MD AD1MD(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 T5MD: Timer5 Module Dis
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED) bit 3 SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2 C2MD: ECAN2 Module Disable bit 1 = ECAN2 module is disabled 0 = ECAN2 module is enabled bit 1 C1MD: ECAN1 Module Disable bit 1 = ECAN1 module is disabled 0 = ECAN1 module is enabled bit 0 AD1MD: ADC1 Module Disable bit(1) 1 = ADC1 module is disabled 0 = ADC1 module is enabled Note 1: The PCFGx
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 IC8MD: Input Ca
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 (CONTINUED) bit 3 OC4MD: Output Compare 4 Module Disable bit 1 = Output Compare 4 module is disabled 0 = Output Compare 4 module is enabled bit 2 OC3MD: Output Compare 3 Module Disable bit 1 = Output Compare 3 module is disabled 0 = Output Compare 3 module is enabled bit 1 OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled bit 0 OC1MD:
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 T9MD T8MD T7MD T6MD — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — I2C2MD AD2MD(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 T9MD: Timer9 Module Disable bit 1 = Timer9 module is disabled 0 = Timer9 mo
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dsPIC33FJXXXMCX06A/X08A/X10A 11.0 I/O PORTS Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/ X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “I/O Ports” (DS70193) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
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dsPIC33FJXXXMCX06A/X08A/X10A 11.2 Open-Drain Configuration 11.4 In addition to the PORT, LAT and TRIS registers for data control, some port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g.
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dsPIC33FJXXXMCX06A/X08A/X10A 11.6 1. 2. In some cases, certain pins as defined in TABLE 26-9: “DC Characteristics: I/O Pin Input Specifications” under “Injection Current”, have internal protection diodes to VDD and VSS. The term “Injection Current” is also referred to as “Clamp Current”.
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dsPIC33FJXXXMCX06A/X08A/X10A 12.0 Timer1 also supports the following features: TIMER1 • Timer gate operation • Selectable prescaler settings • Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit Period register match or falling edge of external gate signal Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/ X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 R/W-0 TCKPS<1:0> U-0 R/W-0 R/W-0 U-0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Rea
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dsPIC33FJXXXMCX06A/X08A/X10A 13.0 TIMER2/3, TIMER4/5, TIMER6/7 AND TIMER8/9 Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/ X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 11. “Timers” (DS70205) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
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dsPIC33FJXXXMCX06A/X08A/X10A TIMER2/3 (32-BIT) BLOCK DIAGRAM(1) FIGURE 13-1: T2CK 1x Gate Sync 01 TCY 00 TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 TGATE TCS TGATE Q 1 Set T3IF Q D CK 0 PR3 ADC Event Trigger(2) Equal PR2 Comparator MSb LSb TMR3 Reset TMR2 Sync 16 Read TMR2 Write TMR2 16 TMR3HLD 16 16 Data Bus<15:0> Note 1: 2: The 32-Bit Timer Control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 13-2: TIMER2 (16-BIT) BLOCK DIAGRAM TON T2CK TCKPS<1:0> 2 1x Gate Sync Prescaler 1, 8, 64, 256 01 00 TGATE TCS TCY 1 Set T2IF Q D Q CK TGATE 0 Reset Equal TMR2 Sync Comparator PR2  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 13-1: TxCON (T2CON, T4CON, T6CON OR T8CON) CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 R/W-0 TCKPS<1:0> R/W-0 U-0 R/W-0 U-0 T32 — TCS(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timerx On bit When T32 = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 3
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 13-2: TyCON (T3CON, T5CON, T7CON OR T9CON) CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL(2) — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE(1) R/W-0 R/W-0 TCKPS<1:0>(1) U-0 U-0 R/W-0 U-0 — — TCS(1,3) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-b
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dsPIC33FJXXXMCX06A/X08A/X10A NOTES: DS70594D-page 172  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A 14.0 1. INPUT CAPTURE Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/ X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. “Input Capture” (DS70198) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
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dsPIC33FJXXXMCX06A/X08A/X10A 14.
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dsPIC33FJXXXMCX06A/X08A/X10A 15.0 The output compare module can select either Timer2 or Timer3 for its time base. The module compares the value of the timer with the value of one or two Compare registers depending on the operating mode selected. The state of the output pin changes when the timer value matches the Compare register value. The output compare module generates either a single output pulse, or a sequence of output pulses, by changing the state of the output pin on the compare match events.
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dsPIC33FJXXXMCX06A/X08A/X10A 15.1 application must disable the associated timer when writing to the Output Compare Control registers to avoid malfunctions. Output Compare Modes Configure the Output Compare modes by setting the appropriate Output Compare Mode bits (OCM<2:0>) in the Output Compare Control register (OCxCON<2:0>). Table 15-1 lists the different bit settings for the Output Compare modes. Figure 15-2 illustrates the output compare operation for various modes.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 15-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1, 2) U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — OCSIDL — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0, HC R/W-0 — — — OCFLT OCTSEL R/W-0 R/W-0 R/W-0 OCM<2:0> bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’
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dsPIC33FJXXXMCX06A/X08A/X10A NOTES: DS70594D-page 178  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A 16.0 MOTOR CONTROL PWM MODULE Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/ X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. “Motor Control PWM” (DS70187) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 16-1: PWM MODULE BLOCK DIAGRAM PWMxCON1 PWM Enable and Mode SFRs PWMxCON2 PxDTCON1 Dead-Time Control SFRs PxDTCON2 PxFLTACON Fault Pin Control SFRs PxFLTBCON PxOVDCON PWM Manual Control SFR PWM Generator 4 16-Bit Data Bus PxDC4 Buffer PxDC4 Comparator PWM Generator 3 PxTMR Channel 4 Dead-Time Generator and Override Logic PWM4H Channel 3 Dead-Time Generator and Override Logic PWM3H PWM4L Output PWM3L Driver Comparator PWM Generator 2 Channel 2 Dead-Time
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 16-1: PxTCON: PWMx TIME BASE CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 PTEN — PTSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTOPS<3:0> R/W-0 R/W-0 PTCKPS<1:0> R/W-0 PTMOD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTEN: PWM Time Base Timer Enable bit 1 = PWM time base is on
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 16-2: R-0 PxTMR: PWMx TIMER COUNT VALUE REGISTER R/W-0 R/W-0 R/W-0 PTDIR R/W-0 R/W-0 R/W-0 R/W-0 PTMR<14:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTMR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTDIR: PWM Time Base Count Direction Status bit (read-only) 1 = PWM time base is counting down
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 16-4: R/W-0 PxSECMP: PWMx SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 SEVTDIR(1) R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<14:8>(2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SEVTDIR: Special Event Trigger Time Base Direction bit(1) 1 = A Speci
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 16-5: PWMxCON1: PWMx CONTROL REGISTER 1 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — PMOD4 PMOD3 PMOD2 PMOD1 bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PEN4H(1) PEN3H(1) PEN2H(1) PEN1H(1) PEN4L(1) PEN3L(1) PEN2L(1) PEN1L(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimpleme
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 16-6: PWMxCON2: PWMx CONTROL REGISTER 2 U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 SEVOPS<3:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — IUE OSYNC UDIS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 SEVOPS<3:0>: PWM Special Event Trigger Outp
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 16-7: R/W-0 PxDTCON1: PWMx DEAD-TIME CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 DTBPS<1:0> R/W-0 R/W-0 R/W-0 R/W-0 DTB<5:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 DTAPS<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTA<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 DTBPS<1:0>: Dead-Time Unit B Prescale Select bits 11 = Clock period f
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 16-8: PxDTCON2: PWMx DEAD-TIME CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTS4A DTS4I DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 DTS4A: Dead-Time Select for PWM4
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 16-9: PxFLTACON: PWMx FAULT A CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FAOV4H FAOV4L FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L bit 15 bit 8 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTAM — — — FAEN4 FAEN3 FAEN2 FAEN1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 FAOVxH<4:1>:F
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 16-10: PxFLTBCON: PWMx FAULT B CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FBOV4H FBOV4L FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L bit 15 bit 8 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTBM — — — FBEN4(1) FBEN3(1) FBEN2(1) FBEN1(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 FB
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 16-11: PxOVDCON: PWMx OVERRIDE CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 POVD4H POVD4L POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POUT4H POUT4L POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 16-12: PxDC1: PWMx DUTY CYCLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC1<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC1<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PDC1<15:0>: PWM Duty Cycle #1 Value bits REGISTER 16-13: PxDC2: PWMx DUTY CYCLE REGISTER 2 R/W-0 R/W
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 16-14: PxDC3: PWMx DUTY CYCLE REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC3<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC3<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PDC3<15:0>: PWM Duty Cycle #3 Value bits REGISTER 16-15: PxDC4: PWMx DUTY CYCLE REGISTER 4 R/W-0 R/W
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dsPIC33FJXXXMCX06A/X08A/X10A 17.0 This section describes the Quadrature Encoder Interface (QEI) module and associated operational modes. The QEI module provides the interface to incremental encoders for obtaining mechanical position data. QUADRATURE ENCODER INTERFACE (QEI) MODULE Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/X08A/ X10A family of devices. However, it is not intended to be a comprehensive reference source.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 17-1: QEIxCON: QEIx CONTROL REGISTER R/W-0 U-0 R/W-0 R-0 R/W-0 CNTERR — QEISIDL INDEX UPDN R/W-0 R/W-0 R/W-0 QEIM<2:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 SWPAB PCDOUT TQGATE R/W-0 R/W-0 TQCKPS<1:0> R/W-0 R/W-0 R/W-0 POSRES TQCS UPDN_SRC(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CNTERR: Count Error Stat
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 17-1: QEIxCON: QEIx CONTROL REGISTER (CONTINUED) bit 4-3 TQCKPS<1:0>: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value (Prescaler utilized for 16-Bit Timer mode only.) bit 2 POSRES: Position Counter Reset Enable bit 1 = Index pulse resets position counter 0 = Index pulse does not reset position counter (Bit only applies when QEIM<2:0> = 100 or 110.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 17-2: DFLTxCON: DIGITAL FILTER x CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 IMV<2:0> CEID bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 U-0 U-0 QEOUT QECK<2:0> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 IMV<1:0>: Index Match Value bits These bits
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dsPIC33FJXXXMCX06A/X08A/X10A 18.0 peripheral devices may be serial EEPROMs, shift registers, display drivers, ADC, etc. The SPI module is compatible with SPI and SIOP from Motorola®. SERIAL PERIPHERAL INTERFACE (SPI) Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/X08A/ X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 18.
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dsPIC33FJXXXMCX06A/X08A/X10A 18.1 1. In Frame mode, if there is a possibility that the master may not be initialized before the slave: a) If FRMPOL (SPIxCON2<13>) = 1, use a pull-down resistor on SSx. b) If FRMPOL = 0, use a pull-up resistor on SSx. Note: 2. 5. This will insure that during power-up and initialization the master/slave will not lose sync due to an errant SCK transition that would cause the slave to accumulate data shift errors for both transmit and receive appearing as corrupted data.
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dsPIC33FJXXXMCX06A/X08A/X10A 18.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 18-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 SSEN(3) CKP MSTEN R/W-0 R/W-0 R/W-0 R/W-0 SPRE<2:0>(2) R/W-0 PPRE<1:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 18-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(2) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(2) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: 2: 3: The CKE bit is not used in the Framed SPI modes.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 18-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — FRMDLY — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as f
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dsPIC33FJXXXMCX06A/X08A/X10A 19.0 INTER-INTEGRATED CIRCUIT (I2C™) Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/X08A/ X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. “Inter-Integrated Circuit (I2C™)” (DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 19-1: I2C™ BLOCK DIAGRAM (X = 1 OR 2) Internal Data Bus I2CxRCV SCLx Read Shift Clock I2CxRSR LSb SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSb Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read TCY/2 DS70594D-page 204  20
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dsPIC33FJXXXMCX06A/X08A/X10A 19.2 2 C Resources 19.3 Many useful resources related to I2C are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 19.2.1 I2C Control Registers I2CxCON and I2CxSTAT are control and status registers, respectively. The I2CxCON register is readable and writable.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 19-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Hardware Settable bit HC = Hardware Clearable bit -n = Value at POR ‘1’ = Bit i
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 19-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that will be transmitted when the software initiates an Acknowledge sequence.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 R/C-0, HS IWCOL bit 8 R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC I2COV D_A P R-0, HSC R-0, HSC R-0, HSC R_W RBF TBF S bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit C = Clearable bit -n = Val
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 19-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit
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dsPIC33FJXXXMCX06A/X08A/X10A 20.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/ X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
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dsPIC33FJXXXMCX06A/X08A/X10A 20.1 1. 2. UART Helpful Tips In multi-node direct-connect UART networks, UART receive inputs react to the complementary logic level defined by the URXINV bit (UxMODE<4>), which defines the idle state, the default of which is logic high, (i.e., URXINV = 0).
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dsPIC33FJXXXMCX06A/X08A/X10A 20.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 20-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 URXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 HC R/W-0 R-0 R-1 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN(1) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 URXISEL<1:0> R/W-0 R-1 R-0 R-0 R/C-0 R-0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ C = Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is c
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bits 11 = Interrupt is set on the UxRSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on the UxRSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive buffer.
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dsPIC33FJXXXMCX06A/X08A/X10A 21.0 ENHANCED CAN MODULE Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/ X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. “Enhanced Controller Area Network (ECAN™)” (DS70185) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 21-1: ECAN™ TECHNOLOGY MODULE BLOCK DIAGRAM RXF15 Filter RXF14 Filter RXF13 Filter RXF12 Filter DMA Controller RXF11 Filter RXF10 Filter RXF9 Filter RXF8 Filter TRB7 TX/RX Buffer Control Register RXF7 Filter TRB6 TX/RX Buffer Control Register RXF6 Filter TRB5 TX/RX Buffer Control Register RXF5 Filter TRB4 TX/RX Buffer Control Register RXF4 Filter TRB3 TX/RX Buffer Control Register RXF3 Filter TRB2 TX/RX Buffer Control Register RXF2 Filter RXM2 Mask TRB1 TX
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dsPIC33FJXXXMCX06A/X08A/X10A 21.3 Modes of Operation The CAN module can operate in one of several operation modes selected by the user. These modes include: • • • • • • Initialization Mode Disable Mode Normal Operation Mode Listen Only Mode Listen All Messages Mode Loopback Mode Modes are requested by setting the REQOP<2:0> bits (CiCTRL1<10:8>). Entry into a mode is Acknowledged by monitoring the OPMODE<2:0> bits (CiCTRL1<7:5>).
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-1: CiCTRL1: ECAN™ CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 r-0 — — CSIDL ABAT — R/W-1 R/W-0 R/W-0 REQOP<2:0> bit 15 bit 8 R-1 R-0 R-0 OPMODE<2:0> U-0 R/W-0 U-0 U-0 R/W-0 — CANCAP — — WIN bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CSIDL: Stop in
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-2: CiCTRL2: ECAN™ CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R-0 R-0 R-0 R-0 R-0 DNCNT<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 DNCNT<4:0>: DeviceNet™ Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compar
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-3: CiVEC: ECAN™ INTERRUPT CODE REGISTER U-0 U-0 U-0 — — — R-0 R-0 R-0 R-0 R-0 FILHIT<4:0> bit 15 bit 8 U-0 R-1 R-0 R-0 — R-0 R-0 R-0 R-0 ICODE<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 FILHIT<4:0>: Filter Hit Number bits 10000-11111 = Reserved 01111 = Filter 15 • • • 00001 = Filt
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-4: R/W-0 CiFCTRL: ECAN™ FIFO CONTROL REGISTER R/W-0 R/W-0 DMABS<2:0> U-0 U-0 U-0 U-0 U-0 — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSA<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 DMABS<2:0>: DMA Buffer Size bits 111 = Reserved 110 = 32 buffers in DMA RAM 101 = 24 buffers in DMA RAM 100 =
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-5: CiFIFO: ECAN™ FIFO STATUS REGISTER U-0 U-0 — — R-0 R-0 R-0 R-0 R-0 R-0 FBP<5:0> bit 15 bit 8 U-0 U-0 — — R-0 R-0 R-0 R-0 R-0 R-0 FNRB<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FBP<5:0>: FIFO Write Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer • • • 000001 = TRB
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-6: CiINTF: ECAN™ INTERRUPT FLAG REGISTER U-0 — bit 15 U-0 — R-0 TXBO R-0 TXBP R-0 RXBP R-0 TXWAR R-0 RXWAR R-0 EWARN bit 8 R/C-0 IVRIF bit 7 R/C-0 WAKIF R/C-0 ERRIF U-0 — R/C-0 FIFOIF R/C-0 RBOVIF R/C-0 RBIF R/C-0 TBIF bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit ‘1’ = Bit is set C = Clearable bit U = Unimplemented bit
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-7: CiINTE: ECAN™ INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 IVRIE: Invalid Message Interrupt Enable bit
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-8: R-0 CiEC: ECAN™ TRANSMIT/RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 TERRCNT<7:0> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RERRCNT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 TERRCNT<7:0>: Transmit Error Count bits bit 7-0 RERRCNT<7:0>: Receive Error Count bits  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-9: CiCFG1: ECAN™ BAUD RATE CONFIGURATION REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SJW<1:0> R/W-0 R/W-0 R/W-0 BRP<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-6 SJW<1:0>: Synchronization Jump Width bits 11 = Length is 4 x T
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-10: CiCFG2: ECAN™ BAUD RATE CONFIGURATION REGISTER 2 U-0 R/W-x U-0 U-0 U-0 — WAKFIL — — — R/W-x R/W-x R/W-x SEG2PH<2:0> bit 15 bit 8 R/W-x R/W-x SEG2PHTS SAM R/W-x R/W-x R/W-x SEG1PH<2:0> R/W-x R/W-x R/W-x PRSEG<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 WAKFIL: S
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-11: CiFEN1: ECAN™ ACCEPTANCE FILTER ENABLE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 1
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-12: CiBUFPNT1: ECAN™ FILTER 0-3 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F3BP<3:0> R/W-0 R/W-0 R/W-0 F2BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F1BP<3:0> R/W-0 R/W-0 R/W-0 F0BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 F3BP<3:0>: RX Buffer Written when Filter 3 Hits bits 1111 = Filter hits received
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-13: CiBUFPNT2: ECAN™ FILTER 4-7 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F7BP<3:0> R/W-0 R/W-0 R/W-0 F6BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F5BP<3:0> R/W-0 R/W-0 R/W-0 F4BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 F7BP<3:0>: RX Buffer Written when Filter 7 Hits bits 1111 = Filter hits received
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-14: CiBUFPNT3: ECAN™ FILTER 8-11 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F11BP<3:0> R/W-0 R/W-0 R/W-0 F10BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F9BP<3:0> R/W-0 R/W-0 R/W-0 F8BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 F11BP<3:0>: RX Buffer Written when Filter 11 Hits bits 1111 = Filter hits rec
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-15: CiBUFPNT4: ECAN™ FILTER 12-15 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F15BP<3:0> R/W-0 R/W-0 R/W-0 F14BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F13BP<3:0> R/W-0 R/W-0 R/W-0 F12BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 F15BP<3:0>: RX Buffer Written when Filter 15 Hits bits 1111 = Filter hits
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-16: R/W-x CiRXFnSID: ECAN™ ACCEPTANCE FILTER n STANDARD IDENTIFIER (n = 0, 1, ...
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-18: CiFMSKSEL1: ECAN™ FILTER 7-0 MASK SELECTION REGISTER R/W-0 R/W-0 F7MSK<1:0> R/W-0 R/W-0 R/W-0 F6MSK<1:0> R/W-0 R/W-0 F5MSK<1:0> R/W-0 F4MSK<1:0> bit 15 bit 8 R/W-0 R/W-0 F3MSK<1:0> R/W-0 R/W-0 R/W-0 F2MSK<1:0> R/W-0 R/W-0 F1MSK<1:0> R/W-0 F0MSK<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 F7MSK<1:0>: Mask Source for
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-19: CiFMSKSEL2: ECAN™ FILTER 15-8 MASK SELECTION REGISTER R/W-0 R/W-0 F15MSK<1:0> bit 15 R/W-0 R/W-0 F14MSK<1:0> R/W-0 R/W-0 F13MSK<1:0> R/W-0 R/W-0 F12MSK<1:0> bit 8 R/W-0 R/W-0 F11MSK<1:0> bit 7 R/W-0 R/W-0 F10MSK<1:0> R/W-0 R/W-0 F9MSK<1:0> R/W-0 R/W-0 F8MSK<1:0> bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-12 bit 11-10 bit 9-8 bit 7-6 bit 5-4 bit 3-2 bit 1-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-20: CiRXMnSID: ECAN™ ACCEPTANCE FILTER MASK n STANDARD IDENTIFIER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID<10:3> bit 15 bit 8 R/W-x R/W-x R/W-x SID<2:0> U-0 R/W-x U-0 — MIDE — R/W-x R/W-x EID<17:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 SID<10:0>: Standard Identifier bits 1 = Include bit, SI
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-22: CiRXFUL1: ECAN™ RECEIVE BUFFER FULL REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 bit 7 bit 0 C= Clearable bit Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit i
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-24: CiRXOVF1: ECAN™ RECEIVE BUFFER OVERFLOW REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 bit 7 bit 0 C= Clearable bit Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = B
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dsPIC33FJXXXMCX06A/X08A/X10A CiTRmnCON: ECAN™ TX/RX BUFFER mn CONTROL REGISTER (m = 0,2,4,6; n = 1,3,5,7) REGISTER 21-26: R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 TXENn TXABTn TXLARBn TXERRn TXREQn RTRENn R/W-0 R/W-0 TXnPRI<1:0> bit 15 bit 8 R/W-0 R-0 TXENm TXABTm(1) R-0 R-0 TXLARBm(1) TXERRm(1) R/W-0 R/W-0 TXREQm RTRENm R/W-0 R/W-0 TXmPRI<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is
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dsPIC33FJXXXMCX06A/X08A/X10A Note: The buffers, SID, EID, DLC, Data Field and Receive Status registers, are located in DMA RAM. REGISTER 21-27: CiTRBnSID: ECAN™ BUFFER n STANDARD IDENTIFIER (n = 0, 1, ...
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-29: CiTRBnDLC: ECAN™ BUFFER n DATA LENGTH CONTROL (n = 0, 1, ...
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 21-31: CiTRBnSTAT: ECAN™ RECEIVE BUFFER n STATUS (n = 0, 1, ...
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dsPIC33FJXXXMCX06A/X08A/X10A 22.0 10-BIT/12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/X08A/ X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 22-1: ADCx MODULE BLOCK DIAGRAM AN0 ANy(3) S/H0 Channel Scan + CH0SA<4:0> CH0 CH0SB<4:0> - CSCNA AN1 VREFL CH0NA CH0NB AN0 AN3 S/H1 VREF+(1) AVDD VREF- (1) AVSS + - CH123SA CH123SB CH1(2) AN6 AN9 VCFG<2:0> VREFL VREFH VREFL CH123NA CH123NB SAR ADC ADC1BUF0 AN1 AN4 S/H2 + CH123SA CH123SB CH2(2) - AN7 AN10 VREFL CH123NA CH123NB AN2 AN5 S/H3 + CH123SA CH123SB CH3(2) - AN8 AN11 VREFL CH123NA CH123NB Alternate Input Selection Note 1: 2: 3: VREF+
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADxCON3<15> ADC Internal RC Clock(2) 1 TAD ADxCON3<5:0> 0 6 TOSC(1) X2 TCY ADC Conversion Clock Multiplier 1, 2, 3, 4, 5,..., 64 Note 1: Refer to Figure 9-2 for the derivation of FOSC when the PLL is enabled. If the PLL is not used, FOSC is equal to the clock source frequency, TOSC = 1/FOSC. 2: See the ADC electrical specifications for the exact RC clock value.  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A 22.4 1. 2. 3. 4. 5. ADC Helpful Tips The SMPI<3:0> (AD1CON2<5:2>) control bits: a) Determine when the ADC interrupt flag is set and an interrupt is generated if enabled. b) When the CSCNA bit (AD1CON2<10>) is set to ‘1’, determines when the ADC analog scan channel list defined in the AD1CSSL/ AD1CSSH registers starts over from the beginning.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 22-1: ADxCON1: ADCx CONTROL REGISTER 1 (where x = 1 or 2) R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 ADON — ADSIDL ADDMABM — AD12B R/W-0 R/W-0 FORM<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 SSRC<2:0> U-0 R/W-0 R/W-0 R/W-0, HC,HS R/C-0, HC, HS — SIMSAM ASAM SAMP DONE bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ C= Clearable bit -n = Value at POR ‘1
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 22-1: ADxCON1: ADCx CONTROL REGISTER 1 (where x = 1 or 2) (CONTINUED) bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x) When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 22-2: R/W-0 ADxCON2: ADCx CONTROL REGISTER 2 (where x = 1 or 2) R/W-0 R/W-0 VCFG<2:0> U-0 U-0 R/W-0 — — CSCNA R/W-0 R/W-0 CHPS<1:0> bit 15 bit 8 R-0 U-0 BUFS — R/W-0 R/W-0 R/W-0 R/W-0 SMPI<3:0> R/W-0 R/W-0 BUFM ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 x = Bit is unknown VCFG<2:0>: Converter Voltage Reference Configu
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 22-2: bit 0 ADxCON2: ADCx CONTROL REGISTER 2 (CONTINUED) (where x = 1 or 2) ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A DS70594D-page 252  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 22-3: ADxCON3: ADCx CONTROL REGISTER 3 R/W-0 U-0 U-0 ADRC — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SAMC<4:0>(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock 0 = Clock derived from system clock bit 14-13
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 22-4: ADxCON4: ADCx CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 DMABL<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 DMABL<2:0>: Selects Number of DMA Buffer Locations per Analog
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 22-5: ADxCHS123: ADCx INPUT CHANNEL 1, 2, 3 SELECT REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 CH123NB<1:0> R/W-0 CH123SB bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 CH123NA<1:0> R/W-0 CH123SA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 CH123NB<1
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 22-6: ADxCHS0: ADCx INPUT CHANNEL 0 SELECT REGISTER R/W-0 U-0 U-0 CH0NB — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0SB<4:0> bit 15 bit 8 R/W-0 U-0 U-0 CH0NA — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0SA<4:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit Same defini
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 22-7: ADxCSSH: ADCx INPUT SCAN SELECT REGISTER HIGH(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS23 CSS22 CSS21 CSS20 CSS19 CSS18 CSS17 CSS16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is un
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dsPIC33FJXXXMCX06A/X08A/X10A REGISTER 22-9: ADxPCFGH: ADCx PORT CONFIGURATION REGISTER HIGH(1,2,3,4) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG31 PCFG30 PCFG29 PCFG28 PCFG27 PCFG26 PCFG25 PCFG24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG23 PCFG22 PCFG21 PCFG20 PCFG19 PCFG18 PCFG17 PCFG16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared b
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dsPIC33FJXXXMCX06A/X08A/X10A 23.0 SPECIAL FEATURES 23.1 Configuration Bits dsPIC33FJXXXMCX06A/X08A/X10A devices provide nonvolatile memory implementation for device configuration bits. Refer to Section 25. “Device Configuration” (DS70194) of the “dsPIC33F/PIC24H Family Reference Manual”, for more information on this implementation. Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/X08A/ X10A family of devices. However, it is not intended to be a comprehensive reference source.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 23-2: Bit Field CONFIGURATION BITS DESCRIPTION Register RTSP Effect Description BWRP FBS Immediate Boot Segment Program Flash Write Protection bit 1 = Boot segment may be written 0 = Boot segment is write-protected BSS<2:0> FBS Immediate Boot Segment Program Flash Code Protection Size bits x11 = No boot program Flash segment Boot space is 1K IW less VS: 110 = Standard security; boot program Flash segment starts at end of VS, ends at 0007FEh 010 = High security; bo
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 23-2: Bit Field SSS<2:0> CONFIGURATION BITS DESCRIPTION (CONTINUED) Register FSS RTSP Effect Description Immediate Secure Segment Program Flash Code Protection Size bits (FOR 128K and 256K DEVICES) X11 = No secure program Flash segment Secure space is 8K IW less BS: 110 = Standard security; secure program Flash segment starts at end of BS, ends at 0x003FFE 010 = High security; secure program Flash segment starts at end of BS, ends at 0x003FFE Secure space is 16K IW les
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 23-2: Bit Field CONFIGURATION BITS DESCRIPTION (CONTINUED) Register GWRP FGS RTSP Effect Description Immediate General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected IESO FOSCSEL Immediate Two-Speed Oscillator Start-up Enable bit 1 = Start-up device with FRC, then automatically switch to the user-selected oscillator source when ready 0 = Start-up device with user-selected oscillator source FNOSC<
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 23-2: Bit Field CONFIGURATION BITS DESCRIPTION (CONTINUED) Register RTSP Effect Description PWMPIN FPOR Immediate Motor Control PWM Module Pin Mode bit 1 = PWM module pins controlled by PORT register at device Reset (tri-stated) 0 = PWM module pins controlled by PWM module at device Reset (configured as output pins) HPOL FPOR Immediate Motor Control PWM High Side Polarity bit 1 = PWM module high side output pins have active-high output polarity 0 = PWM module high
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dsPIC33FJXXXMCX06A/X08A/X10A 23.2 On-Chip Voltage Regulator All of the dsPIC33FJXXXMCX06A/X08A/X10A devices power their core digital logic at a nominal 2.5V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the dsPIC33FJXXXMCX06A/X08A/X10A family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator provides power to the core from the other VDD pins.
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dsPIC33FJXXXMCX06A/X08A/X10A 23.4 Watchdog Timer (WDT) For dsPIC33FJXXXMCX06A/X08A/X10A devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Configuration bit.
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dsPIC33FJXXXMCX06A/X08A/X10A 23.5 JTAG Interface dsPIC33FJXXXMCX06A/X08A/X10A devices implement a JTAG interface, which supports boundary scan device testing, as well as in-circuit programming. Detailed information on the interface will be provided in future revisions of the document. 23.6 Code Protection and CodeGuard™ Security The dsPIC33FJXXXMCX06A/X08A/X10A devices offer the advanced implementation of CodeGuard™ Security.
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dsPIC33FJXXXMCX06A/X08A/X10A 24.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/X08A/ X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). The dsPIC33F instruction set is identical to that of the dsPIC30F.
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dsPIC33FJXXXMCX06A/X08A/X10A All instructions are a single word, except for certain double-word instructions, which were made doubleword instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 24-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm*Wm Multiplicand and Multiplier working register pair for Square instructions  {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions  {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 working registers {W0..W15} Wnd One of 16 destination working registers {W0...W15} Wns One of 16 source working registers {W0..
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 24-2: Base Instr # 1 2 3 4 5 6 7 8 INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW Assembly Syntax # of # of Words Cycles Description Status Flags Affected ADD Acc Add Accumulators 1 1 ADD f f = f + WREG 1 1 OA,OB,SA,SB C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 24-2: Base Instr # 11 12 13 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSS BTST BTSTS Assembly Syntax Description # of # of Words Cycles Status Flags Affected BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3) None BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 (2 or 3) None BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 24-2: Base Instr # INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax # of # of Words Cycles Description Status Flags Affected 34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None 35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C 36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C 37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 38 GOTO GOTO Expr Go to Address 2 2 None GOTO
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 24-2: Base Instr # 51 52 53 54 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic MUL NEG NOP POP Assembly Syntax PUSH # of # of Words Cycles Status Flags Affected MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None MUL.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 24-2: Base Instr # 71 72 73 74 75 76 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic SL SUB SUBB SUBR SUBBR SWAP Assembly Syntax Description # of # of Words Cycles Status Flags Affected SL f f = Left Shift f 1 1 C,N,OV,Z SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z SUB Acc Subtrac
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dsPIC33FJXXXMCX06A/X08A/X10A 25.
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dsPIC33FJXXXMCX06A/X08A/X10A 25.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use.
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dsPIC33FJXXXMCX06A/X08A/X10A 25.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
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dsPIC33FJXXXMCX06A/X08A/X10A 25.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 25.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
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dsPIC33FJXXXMCX06A/X08A/X10A 26.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJXXXMCX06A/X08A/X10A electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33FJXXXMCX06A/X08A/X10A family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
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dsPIC33FJXXXMCX06A/X08A/X10A 26.1 DC Characteristics TABLE 26-1: OPERATING MIPS vs. VOLTAGE Param No. VDD Range (in Volts) — Note 1: dsPIC33FJXXXMCX06A/X08A/X10A (1) -40°C to +85°C 40 (1) -40°C to +125°C 40 VBOR-3.6V — VBOR-3.6V Max MIPS Temp Range (in °C) Device is functional at VBORMIN < VDD < VDDMIN. Analog modules such as the ADC will have degraded performance. Device functionality is tested but not characterized.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions Operating Voltage DC10 Supply Voltage VDD — 3.0 — 3.6 V — DC12 VDR RAM Data Retention Voltage(2) 1.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Parameter No.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Parameter No.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Parameter No.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Parameter No.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Typ(1) Max Units Conditions Input Low Voltage DI10 I/O Pins VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 I/O Pins with OSC1 or SOSCI VSS — 0.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param Symbol No.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param Symbol No. DO10 DO20 VOL VOH Characteristic Min Typ Max Units Conditions Output Low Voltage I/O Pins: 2x Sink Driver Pins - All pins not defined by 4x or 8x driver pins — — 0.4 V IOL  3 mA, VDD = 3.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-11: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Characteristic(1) Param. Symbol Min(1) Max(1) Typ Units BOR Event on VDD Transition High-to-Low 2.40 — 2.55 BO10 VBOR Note 1: Parameters are for design guidance only and are not tested in manufacturing.
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dsPIC33FJXXXMCX06A/X08A/X10A 26.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC33FJXXXMCX06A/X08A/X10A AC characteristics and timing parameters. TABLE 26-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Operating voltage VDD range as described in Table 26-1.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 OS30 OS30 Q3 Q4 OSC1 OS20 OS31 OS31 OS25 CLKO OS41 OS40 TABLE 26-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min Typ(1) Max Units OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range 0.8 — 8.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-3: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 26-1 for load conditions. TABLE 26-20: I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-4: VDD RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 MCLR SY10 Internal POR PWRT Time-out OSC Time-out SY11 SY30 Internal Reset Watchdog Timer Reset SY13 SY20 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 26-1 for load conditions. DS70594D-page 294  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol No.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-5: TIMER1, 2, 3, 4, 5, 6, 7, 8 AND 9 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 OS60 Tx20 TMRx Note: Refer to Figure 26-1 for load conditions. TABLE 26-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-23: TIMER2, TIMER4, TIMER6 AND TIMER8 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-6: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure 26-1 for load conditions. TABLE 26-25: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-8: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx Active Tri-state TABLE 26-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-9: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS MP30 FLTA/B MP20 PWMx FIGURE 26-10: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure 26-1 for load conditions. TABLE 26-28: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-11: QEA/QEB INPUT CHARACTERISTICS TQ36 QEA (input) TQ30 TQ31 TQ35 QEB (input) TQ41 TQ40 TQ30 TQ31 TQ35 QEB Internal TABLE 26-29: QUADRATURE DECODER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-12: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS QEA (input) QEB (input) Ungated Index TQ50 TQ51 Index Internal TQ55 Position Counter Reset TABLE 26-30: QEI INDEX PULSE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Symbol TQ50 TqiL TQ51 TQ55 Note 1: 2: Standard Operating Conditions: 3.0V to 3.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-13: TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS QEB TQ11 TQ10 TQ15 TQ20 POSCNT TABLE 26-31: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-32: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY Standard Operating Conditions: 3.0V to 3.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-33: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-16: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = X, SMP = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP30, SP31 SP40 SDIx LSb MSb In LSb In Bit 14 - - - -1 SP41 Note: Refer to Figure 26-1 for load conditions. TABLE 26-34: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-17: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 SP30, SP31 SDIx MSb In LSb SP30, SP31 LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 26-1 for load conditions. TABLE 26-35: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.4V to 3.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-18: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 26-1 for load conditions. DS70594D-page 308  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-19: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 SP52 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 26-1 for load conditions. DS70594D-page 310  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-37: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-20: SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 26-1 for load conditions. DS70594D-page 312  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-38: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-21: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 26-1 for load conditions. DS70594D-page 314  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-39: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-22: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 26-1 for load conditions. FIGURE 26-23: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 26-1 for load conditions. DS70594D-page 316  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-40: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param Symbol No.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-24: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition FIGURE 26-25: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out DS70594D-page 318  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-41: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No. IS10 IS11 IS20 IS21 IS25 IS26 IS30 IS31 IS33 IS34 IS40 IS45 IS50 Note Symbol TLO:SCL THI:SCL Characteristic Clock Low Time Clock High Time Min Max Units 100 kHz mode 4.7 — s 400 kHz mode 1.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-26: CAN MODULE I/O TIMING CHARACTERISTICS CiTx Pin (output) New Value Old Value CA10 CA11 CiRx Pin (input) CA20 TABLE 26-42: ECAN™ TECHNOLOGY MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-43: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min. Typ Max. Units Conditions Lesser of VDD + 0.3 or 3.6 V VSS + 0.3 V — — Device Supply AD01 AVDD Module VDD Supply AD02 AVSS Module VSS Supply AD05 VREFH Reference Voltage High Greater of VDD – 0.3 or 3.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-44: ADC MODULE SPECIFICATIONS (12-BIT MODE)(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-45: ADC MODULE SPECIFICATIONS (10-BIT MODE)(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions ADC Accuracy (10-Bit Mode) – Measurements with External VREF+/VREFAD20c Nr Resolution 10 data bits bits — AD21c INL Integral Nonlinearity -1.5 — +1.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-27: ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 TSAMP AD55 CONV ADxIF Buffer(0) 1 2 3 4 5 6 7 8 9 1 – Software sets ADxCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 16. “10/12-bit ADC with DMA” in the “dsPIC33F Family Reference Manual”. 3 – Software clears ADxCON.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-46: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions Clock Parameters AD50a TAD ADC Clock Period AD51a tRC ADC Internal RC Oscillator Period 117.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-28: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 AD55 TSAMP AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets ADxCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 16.
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dsPIC33FJXXXMCX06A/X08A/X10A FIGURE 26-29: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Execution Set ADON SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc TSAMP AD55 TSAMP AD55 TCONV CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 – Software sets ADxCON. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 26-47: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C AC CHARACTERISTICS Param Symbol No. Characteristic Typ(1) Min. Max. Units Conditions Clock Parameters AD50b TAD ADC Clock Period 76 — — ns — AD51b tRC ADC Internal RC Oscillator Period — 250 — ns — AD55b tCONV Conversion Time — 12 TAD — — — FCNV Throughput Rate — — 1.
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dsPIC33FJXXXMCX06A/X08A/X10A 27.0 HIGH TEMPERATURE ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJXXXMCX06A/X08A/X10A electrical characteristics for devices operating in an ambient temperature range of -40°C to +150°C. The specifications between -40°C to +150°C are identical to those shown in Section 26.0 “Electrical Characteristics” for operation between -40°C to +125°C, with the exception of the parameters listed in this section.
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dsPIC33FJXXXMCX06A/X08A/X10A 27.1 High Temperature DC Characteristics TABLE 27-1: OPERATING MIPS VS. VOLTAGE VDD Range (in Volts) Characteristic dsPIC33FJXXXMCX06A/X08A/X10A -40°C to +150°C 20 (1) HDC5 Max MIPS Temperature Range (in °C) VBOR to 3.6V Device is functional at VBORMIN < VDD < VDDMIN. Analog modules such as the ADC will have degraded performance. Device functionality is tested but not characterized. Refer to parameter BO10 in Table 26-11 for the minimum and maximum BOR values.
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dsPIC33FJXXXMCX06A/X08A/X10A Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +150°C for High Temperature DC CHARACTERISTICS Parameter No. Typical Max Units 5 A Conditions Power-Down Current (IPD) HDC61c Note 1: 2: 3: 4: 3 Watchdog Timer Current: IWDT(2,4) DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 27-6: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for High Temperature DC CHARACTERISTICS Param.
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dsPIC33FJXXXMCX06A/X08A/X10A 27.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC33FJXXXMCX06A/X08A/X10A AC characteristics and timing parameters for high temperature devices. However, all AC timing specifications in this section are the same as those in Section 26.2 “AC Characteristics and Timing Parameters”, with the exception of the parameters listed in this section. Parameters in this section begin with an H, which denotes High temperature.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 27-9: INTERNAL LPRC ACCURACY AC CHARACTERISTICS Param No. Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +150°C for High Temperature Characteristic Min Typ Max Units -70(2) — +70(2) % Conditions LPRC @ 32.768 kHz (1) HF21 Note 1: 2: LPRC -40°C  TA  +150°C — Change of LPRC frequency as VDD changes. Characterized but not tested.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 27-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +150°C for High Temperature Param No.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 27-14: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param No. HAD08 Note 1: Symbol Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +150°C for High Temperature Characteristic Min Typ Max Units Reference Inputs — 250 600 A — — 50 A These parameters are not characterized or tested in manufacturing.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE 27-17: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +150°C for High Temperature Param No.
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dsPIC33FJXXXMCX06A/X08A/X10A NOTES: DS70594D-page 338  2009-2012 Microchip Technology Inc.
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DC AND AC DEVICE CHARACTERISTICS GRAPHS Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. FIGURE 28-1: VOH – 2x DRIVER PINS -0.040 -0.016 -0.035 3.
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VOL – 2x DRIVER PINS FIGURE 28-7: 0.060 0.020 0.018 3.6V 0.016 3.6V 0.050 3.3V 3.3V 0.014 0.040 3V 0.012 IOL (A) IOL (A) VOL – 8x DRIVER PINS 0.010 0.008 3V 0.030 0.020 0.006 0.004 0.010 0.002 0.000 0.00 1.00 2.00 3.00 0.000 0.00 4.00 1.00 FIGURE 28-6: VOL – 4x DRIVER PINS FIGURE 28-8: 3.00 4.00 VOL – 16x DRIVER PINS 0.120 0.040 0.035 3.6V 0.030 3.6V 0.100 3.3V 0.025 3.3V 0.080 3V IOL (A)  2009-2012 Microchip Technology Inc. IOL (A) 2.00 VOL (V) VOL (V) 0.
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TYPICAL FRC FREQUENCY @ VDD = 3.3V FIGURE 28-10: 7450 50 7400 45 7350 40 Frequency (kHz) Frequency (kHz) TYPICAL LPRC FREQUENCY @ VDD = 3.3V 7300 7250 7200 35 30 25 7150 20 7100 -40 -30 -20 -10 0 10 20 30 40 50 60 70 Temperature Celsius 80 90 100 110 120 40 30 20 10 0 10 20 30 40 50 60 Temperature Celsius 70 80 90 100 110 120 DS70594D-page 341 dsPIC33FJXXXMCX06A/X08A/X10A  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A NOTES: DS70594D-page 342  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 64-Lead QFN (9x9x0.9mm) XXXXXXXXXX XXXXXXXXXX YYWWNNN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN e3 * Note: Example dsPIC33FJ 256MC706A -I/PT e3 0910017 80-Lead TQFP (12x12x1 mm) Legend: XX...
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dsPIC33FJXXXMCX06A/X08A/X10A 29.1 Package Marking Information (Continued) 100-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 100-Lead TQFP (14x14x1mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
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dsPIC33FJXXXMCX06A/X08A/X10A 29.2 Note: Package Details For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70594D-page 346  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 E e E1 N b NOTE 1 12 3 α NOTE 2 A c β φ A2 A1 L1 L 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ±
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dsPIC33FJXXXMCX06A/X08A/X10A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 e E E1 N b NOTE 1 1 23 NOTE 2 α c A φ L β A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV A2 L1 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ±
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dsPIC33FJXXXMCX06A/X08A/X10A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 3) ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 e E1 E b N α NOTE 1 1 23 A NOTE 2 φ c β A2 A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ±
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dsPIC33FJXXXMCX06A/X08A/X10A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A NOTES: DS70594D-page 356  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A APPENDIX A: MIGRATING FROM dsPIC33FJXXXMCX06/ X08/X10 DEVICES TO dsPIC33FJXXXMCX06A/ X08A/X10A DEVICES The dsPIC33FJXXXMCX06A/X08A/X10A devices were designed to enhance the dsPIC33FJXXXMCX06/ X08/X10 families of devices. In general, the dsPIC33FJXXXMCX06A/X08A/X10A devices are backward-compatible with dsPIC33FJXXXMCX06/X08/X10 devices; however, manufacturing differences may cause dsPIC33FJXXXMCX06A/X08A/X10A devices to behave differently from dsPIC33FJXXXMCX06/X08/X10 devices.
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dsPIC33FJXXXMCX06A/X08A/X10A APPENDIX B: REVISION HISTORY Revision A (May 2009) This is the initial released version of the document. Revision B (October 2009) The revision includes the following global update: • Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits. This revision also includes minor typographical and formatting changes throughout the data sheet text.
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dsPIC33FJXXXMCX06A/X08A/X10A Revision C (March 2011) This revision includes typographical and formatting changes throughout the data sheet text. In addition, all instances of VDDCORE have been removed. All other major changes are referenced by their respective section in the following table. TABLE B-2: MAJOR SECTION UPDATES Section Name Section 2.0 “Guidelines for Getting Started with 16-bit Digital Signal Controllers” Update Description Updated the title of Section 2.
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dsPIC33FJXXXMCX06A/X08A/X10A TABLE B-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 26.0 “Electrical Characteristics” Update Description Removed Note 4 from the DC Temperature and Voltage Specifications (see Table 26-4). Updated the maximum value for parameter DI19 and added parameters DI28, DI29, DI60a, DI60b, and DI60c to the I/O Pin Input Specifications (see Table 26-9). Removed Note 2 from the AC Characteristics: Internal RC Accuracy (see Table 26-18).
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dsPIC33FJXXXMCX06A/X08A/X10A Revision D (June 2012) This revision includes typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE B-3: MAJOR SECTION UPDATES Section Name Update Description Section 2.0 “Guidelines for Getting Started Updated the Recommended Minimum Connection (see Figure 2-1). with 16-bit Digital Signal Controllers” Section 9.
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dsPIC33FJXXXMCX06A/X08A/X10A NOTES: DS70594D-page 362  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A INDEX A A/D Converter ................................................................... 245 DMA .......................................................................... 245 Initialization ............................................................... 245 Key Features............................................................. 245 AC Characteristics .................................................... 290, 333 ADC Module......................................................
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dsPIC33FJXXXMCX06A/X08A/X10A ECAN Module ECAN1 Register Map (C1CTRL1.WIN = 0 or 1) ......... 55 ECAN1 Register Map (C1CTRL1.WIN = 0) ................ 55 ECAN1 Register Map (C1CTRL1.WIN = 1) ................ 56 ECAN2 Register Map (C2CTRL1.WIN = 0 or 1) ......... 58 ECAN2 Register Map (C2CTRL1.WIN = 0) .......... 58, 59 ECAN Technology Frame Types ............................................................. 217 Modes of Operation .................................................. 219 Overview ...............
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dsPIC33FJXXXMCX06A/X08A/X10A Pinout I/O Descriptions (table) ............................................ 15 PMD Module Register Map............................................................... 62 POR and Long Oscillator Start-up Times............................ 84 PORTA Register Map............................................................... 60 PORTB Register Map............................................................... 60 PORTC Register Map.......................................................
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dsPIC33FJXXXMCX06A/X08A/X10A IPC13 (Interrupt Priority Control 13) ......................... 125 IPC14 (Interrupt Priority Control 14) ......................... 126 IPC15 (Interrupt Priority Control 15) ......................... 127 IPC16 (Interrupt Priority Control 16) ......................... 128 IPC17 (Interrupt Priority Control 17) ......................... 129 IPC2 (Interrupt Priority Control 2) ............................. 114 IPC3 (Interrupt Priority Control 3) .............................
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dsPIC33FJXXXMCX06A/X08A/X10A Timing Specifications 10-Bit A/D Conversion Requirements ....................... 328 12-Bit A/D Conversion Requirements ....................... 325 CAN I/O Requirements ............................................. 320 I2Cx Bus Data Requirements (Master Mode) ........... 317 I2Cx Bus Data Requirements (Slave Mode) ............. 319 Motor Control PWM Requirements ........................... 300 Output Compare Requirements ................................ 298 PLL Clock............
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dsPIC33FJXXXMCX06A/X08A/X10A NOTES: DS70594D-page 368  2009-2012 Microchip Technology Inc.
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dsPIC33FJXXXMCX06A/X08A/X10A THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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dsPIC33FJXXXMCX06A/X08A/X10A READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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dsPIC33FJXXXMCX06A/X08A/X10A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 256 MC7 10 A T I / PT - XXX Examples: a) Microchip Trademark Architecture Flash Memory Family dsPIC33FJ256MC710ATI/PT: Motor Control dsPIC33, 64-Kbyte program memory, 64-pin, Industrial temperature, TQFP package.
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dsPIC33FJXXXMCX06A/X08A/X10A NOTES: DS70594D-page 372  2009-2012 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.