Datasheet

 2009-2012 Microchip Technology Inc. DS70591E-page 445
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
INDEX
A
AC Characteristics ............................................................ 378
10-Bit, High-Speed ADC ........................................... 406
Internal FRC Accuracy.............................................. 381
Internal LPRC Accuracy............................................ 381
Load Conditions ........................................................ 378
Temperature and Voltage Specifications .................. 378
Alternate Interrupt Vector Table (AIVT) ............................ 123
Arithmetic Logic Unit (ALU)................................................. 39
Assembler
MPASM Assembler................................................... 362
B
Barrel Shifter ....................................................................... 43
Bit-Reversed Addressing .................................................. 102
Example .................................................................... 103
Implementation ......................................................... 102
Sequence Table (16-Entry)....................................... 103
Block Diagrams
16-Bit Timer1 Module................................................ 215
AC-to-DC Power Supply with PFC and 3 Outputs ...... 32
ADC Module with 1 SAR for dsPIC33FJ32GS406,
dsPIC33FJ64GS406 Devices ............................... 311
ADC Module with 2 SARs for dsPIC33FJ32GS606,
dsPIC33FJ64GS606 Devices ............................... 312
ADC Module with 2 SARs for dsPIC33FJ32GS608,
dsPIC33FJ64GS608 Devices ............................... 313
ADC Module with 2 SARs for dsPIC33FJ32GS610,
dsPIC33FJ64GS610 Devices ............................... 314
Boost Converter Implementation ................................ 27
Conceptual High-Speed PWMx ................................ 231
Connections for On-Chip Voltage Regulator............. 349
Digital PFC.................................................................. 27
DMA Top Level System Architecture Using
Dedicated Transaction Bus............................... 178
DSP Engine ................................................................ 40
dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610...................... 18
dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610 CPU Core .... 34
ECANx Module ......................................................... 282
High-Speed Analog Comparator x Module ............... 341
High-Speed PWMx Architecture ............................... 230
I
2
C Module ................................................................ 268
Input Capture x ......................................................... 223
Interleaved PFC .......................................................... 30
Multi-Phase Synchronous Buck Converter ................. 28
Off-Line Ups................................................................ 29
Oscillator System ...................................................... 188
Output Compare Module........................................... 225
Phase-Shifted Full-Bridge Converter .......................... 31
PLL............................................................................ 190
Quadrature Encoder Interface x................................ 257
Reset System............................................................ 115
Shared Port Structure ............................................... 212
Simplified UART Module........................................... 275
Single-Phase Synchronous Buck Converter............... 28
SPI Module ............................................................... 261
Timer2/3/4/5 (32-Bit) ................................................. 219
Type B Timer ............................................................ 217
Type C Timer ............................................................ 217
Watchdog Timer (WDT) ............................................ 350
Brown-out Reset (BOR) .................................... 119, 345, 349
C
C Compilers
MPLAB C18.............................................................. 362
Clock Generation
Auxiliary .................................................................... 191
Reference ................................................................. 191
Clock Switching ................................................................ 199
Enabling.................................................................... 199
Sequence ................................................................. 199
Code Examples
Erasing a Program Memory Page ............................ 113
Initiating a Programming Sequence ......................... 114
Loading Write Buffers ............................................... 114
Port Write/Read ........................................................ 213
PWRSAV Instruction Syntax .................................... 201
Code Protection........................................................ 345, 352
CodeGuard Security ................................................. 345, 352
Configuration Bits ............................................................. 345
Description................................................................ 346
Configuration Register Map .............................................. 345
Configuring Analog Port Pins............................................ 213
CPU
Control Registers........................................................ 36
CPU Clocking System ...................................................... 189
PLL Configuration..................................................... 190
Selection................................................................... 189
Sources .................................................................... 189
Customer Change Notification Service............................. 451
Customer Notification Service .......................................... 451
Customer Support............................................................. 451
D
Data Accumulators and Adder/Subtracter .......................... 41
Data Space Write Saturation ...................................... 43
Overflow and Saturation ............................................. 41
Round Logic ............................................................... 42
Write Back .................................................................. 42
Data Address Space........................................................... 47
Alignment.................................................................... 47
Memory Map for 4-Kbyte RAM Devices ..................... 48
Memory Map for 8-Kbyte RAM Devices ..................... 49
Memory Map for 9-Kbyte RAM Devices ..................... 50
Near Data Space ........................................................ 47
SFR Space ................................................................. 47
Software Stack ........................................................... 99
Width .......................................................................... 47
DC and AC Characteristics
Graphs and Tables ................................................... 421
DC Characteristics
Brown-out Reset (BOR)............................................ 376
Doze Current (I
DOZE)................................................ 372
I/O Pin Input Specifications ...................................... 373
I/O Pin Output Specifications.................................... 375
Idle Current (I
IDLE) .................................................... 370
Internal Voltage Regulator Specifications................. 377
Operating Current (I
DD) ............................................ 368
Operating MIPS vs. Voltage ..................................... 366
Power-Down Current (I
PD)........................................ 371
Program Memory...................................................... 377
Temperature and Voltage Specifications.................. 367