Datasheet

 2009-2012 Microchip Technology Inc. DS70591E-page 345
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
24.0 SPECIAL FEATURES
The dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610 devices include
several features intended to maximize application
flexibility and reliability, and minimize cost through
elimination of external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
• Brown-out Reset (BOR)
24.1 Configuration Bits
The dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610 devices provide
non-volatile memory implementations for device
Configuration bits. Refer to Section 25. “Device
Configuration” (DS70194) in the “dsPIC33F/PIC24H
Family Reference Manual” for more information on this
implementation.
The Configuration bits can be programmed (read
as ‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 0xF80000.
The individual Configuration bit descriptions for the
Configuration registers are shown in Table 24-2.
Note that address, 0xF80000, is beyond the user pro-
gram memory space. It belongs to the configuration
memory space (0x800000-0xFFFFFF), which can only
be accessed using Table Reads and Table Writes.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written again. Changing a
device configuration requires that power to the device
be cycled.
The device Configuration register map is shown in
Table 24-1.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
the “dsPIC33F/PIC24H Family Reference
Manual”. Please see the Microchip web
site (www.microchip.com) for the latest
“dsPIC33F/PIC24H Family Reference
Manual” sections.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
TABLE 24-1: DEVICE CONFIGURATION REGISTER MAP
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0xF80000 FBS
— — — —BSS<2:0>BWRP
0xF80002 RESERVED
— — — — — — — —
0xF80004 FGS — — — — —GSS<1:0>GWRP
0xF80006 FOSCSEL IESO
— — —FNOSC<2:0>
0xF80008 FOSC FCKSM<1:0>
— — — OSCIOFNC POSCMD<1:0>
0xF8000A FWDT FWDTEN WINDIS
— WDTPRE WDTPOST<3:0>
0xF8000C FPOR
— ALTQIO ALTSS1 — —FPWRT<2:0>
0xF8000E FICD Reserved
(1)
Reserved
(1)
JTAGEN — — —ICS<1:0>
0xF80010 FCMP
— — CMPPOL1
(2)
HYST1<1:0>
(2)
CMPPOL0
(2)
HYST0<1:0>
(2)
Legend: — = unimplemented bit, read as ‘0’.
Note 1: These bits are reserved for use by development tools and must be programmed as ‘1’.
2: These bits are reserved on dsPIC33FJXXXGS406 devices and always read as ‘1’.