Datasheet

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS70591E-page 316  2009-2012 Microchip Technology Inc.
bit 3 Unimplemented: Read as ‘0’
bit 2-0 ADCS<2:0>: Analog-to-Digital Conversion Clock Divider Select bits
(1)
111 = FADC/8
110 = FADC/7
101 = FADC/6
100 = FADC/5
011 = FADC/4 (default)
010 = FADC/3
001 = FADC/2
000 = FADC/1
REGISTER 22-1: ADCON: ADC CONTROL REGISTER (CONTINUED)
Note 1: This control bit can only be changed while the ADC is disabled (ADON = 0).
2: This control bit is only active on devices that have one SAR.