Datasheet

 2009-2012 Microchip Technology Inc. DS70591E-page 233
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-1: PTCON: PWM TIME BASE CONTROL REGISTER
R/W-0 U-0 R/W-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0
PTEN — PTSIDL SESTAT SEIEN EIPU
(1)
SYNCPOL
(1)
SYNCOEN
(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SYNCEN
(1)
SYNCSRC<2:0>
(1)
SEVTPS<3:0>
(1)
bit 7 bit 0
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PTEN: PWM Module Enable bit
1 = PWM module is enabled
0 = PWM module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 PTSIDL: PWM Time Base Stop in Idle Mode bit
1 = PWM time base halts in CPU Idle mode
0 = PWM time base runs in CPU Idle mode
bit 12 SESTAT: Special Event Interrupt Status bit
1 = Special Event Interrupt is pending
0 = Special Event Interrupt is not pending
bit 11 SEIEN: Special Event Interrupt Enable bit
1 = Special Event Interrupt is enabled
0 = Special Event Interrupt is disabled
bit 10 EIPU: Enable Immediate Period Updates bit
(1)
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWM cycle boundaries
bit 9 SYNCPOL: Synchronize Input and Output Polarity bit
(1)
1 = SYNCIx/SYNCO1 polarity is inverted (active-low)
0 = SYNCIx/SYNCO1 is active-high
bit 8 SYNCOEN: Primary Time Base Synchronization Enable bit
(1)
1 = SYNCO1 output is enabled
0 = SYNCO1 output is disabled
bit 7 SYNCEN: External Time Base Synchronization Enable bit
(1)
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
bit 6-4 SYNCSRC<2:0>: Synchronous Source Selection bits
(1)
111 = Reserved
101 = Reserved
100 = Reserved
011 = SYNCI4
010 = SYNCI3
001 = SYNCI2
000 = SYNCI1
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.