Datasheet

 2009-2012 Microchip Technology Inc. DS70591E-page 231
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 16-2: SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF THE HIGH-SPEED PWMx
MUX
PTMRx
PDCx
PWMCONx
TRGCONx
PTCON, PTCON2
IOCONx
DTRx
PWMxL
PWMxH
FLTn
(1)
PWM1L
PWM1H
FCLCONx
PHASEx
LEBCONx
MUX
STMRx
SDCx
SPHASEx
ALTDTRx
PWMCAPx
User Override Logic
Current-Limit
PWM Output Mode
Control Logic
Dead-
Logic
Pin
Control
Logic
Fault and
Current-Limit
Logic
PWM Generator 1
FLTn
(1)
PWM Generator 2 – PWM Generator 9
Interrupt
Logic
ADC Trigger
Module Control and Timing
Master Duty Cycle Register
Synchronization
Synchronization
Master PeriodMaster Period
Master Duty CycleMaster Duty Cycle
Secondary PWM
SYNCI4
SYNCI1
SYNCO1
SEVTCMP
Comparator
Special Event Trigger
Special Event
Postscaler
PTPER
PMTMR
Primary Master Time Base
Master Time Base Counter
Special Event Compare Trigger
Comparator
Clock
Prescaler
Comparator
Comparator
Comparator
16-Bit Data Bus
Time
TRIGx
Fault Override Logic
Override Logic
SYNCO2
SEVTCMP
Comparator
Special Event Trigger
Special Event
Postscaler
STPER
SMTMR
Secondary Master Time Base
Master Time Base Counter
Special Event Compare Trigger
Comparator
Clock
Prescaler
DTCMPx
STCON, STCON2
• • •
Comparator
STRIGx
Note 1: n = 1 through 23.
ADC Trigger
MDC