Datasheet

 2009-2012 Microchip Technology Inc. DS70591E-page 165
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-36: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— QEI2IP<2:0> — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— PSESMIP<2:0> — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 QEI2IP<2:0>: QEI2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
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•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11-7 Unimplemented: Read as ‘0’
bit 6-4 PSESMIP<2:0>: PWM Special Event Secondary Match Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
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•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as ‘0’