Datasheet

 2009-2012 Microchip Technology Inc. DS70591E-page 145
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-16: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0
— — — — — QEI1IE PSEMIE —
bit 15 bit 8
U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0
—INT4IEINT3IE— — MI2C2IE SI2C2IE —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10 QEI1IE: QEI1 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 9 PSEMIE: PWM Special Event Match Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 8-7 Unimplemented: Read as ‘0’
bit 6 INT4IE: External Interrupt 4 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 6 INT3IE: External Interrupt 3 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 4-3 Unimplemented: Read as ‘0’
bit 2 MI2C2IE: I2C2 Master Events Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 1 SI2C2IE: I2C2 Slave Events Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 0 Unimplemented: Read as ‘0’