Datasheet

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS70591E-page 442  2009-2012 Microchip Technology Inc.
Revision D (January 2012)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
All occurrences of PGCn and PGDn (where n = 1, 2,
or 3) were updated to: PGECn and PGEDn throughout
the document.
All other changes are referenced by their respective
section in Tab le B- 3 .
TABLE B-3: MAJOR SECTION UPDATES
Section Name Update Description
“16-Bit Digital Signal Controllers with
High-Speed PWM, ADC and
Comparators”
Added 50 MIPS to Operating Range.
Changed the Oscillator frequency range in System Management.
Added the “Referenced Sources” section.
Section 1.0 “Device Overview” Updated the block diagram of the core and peripheral modules (see
Figure 1-1).
Section 2.0 “Guidelines for Getting
Started with 16-Bit Digital Signal
Controllers”
Updated the Recommended Minimum Connection diagram (see
Figure 2-1).
Updated the V
CAP pin capacitor specification in Section 2.3
“Capacitor on Internal Voltage Regulator (V
CAP)”.
Section 4.0 “Memory Organization” Removed IPC20 and updated IFS5, IFS7, IEC5, IEC7, and IPC29 in
the Interrupt Controller Register Map for dsPIC33FJ64GS606 devices
(see Table 4-6).
Removed IPC20 and IPC21 and updated IFS5, IFS7, IEC5, IEC7, and
IPC29 in the Interrupt Controller Register Map for dsPIC33FJ32GS406
and dsPIC33FJ64GS406 devices (see Tab l e 4 - 7 ).
Removed IPC20 and updated IFS5, IFS7, IEC5, IEC7, and IPC29 in
the Interrupt Controller Register Map for dsPIC33FJ32GS606 devices
(see Table 4-10).
Added High-Speed 10-bit ADC Register Map for dsPIC33FJ32GS406
and dsPIC33FJ64GS406 devices (see Tab l e 4 - 3 5 ).
Updated ODCG in PORTG Register Map for dsPIC33FJ32GS610 and
dsPIC33FJ64GS610 devices (see Ta bl e 4 - 5 4 ).
Updated ODCG in PORTG Register Map for dsPIC33FJ32GS608 and
dsPIC33FJ64GS608 devices (see Ta bl e 4 - 5 5 ).
Updated ODCG in PORTG Register Map for dsPIC33FJ32GS406/606
and dsPIC33FJ64GS406/606 devices (see Ta bl e 4 -5 6 ).
Section 9.0 “Oscillator Configuration” Changed the High-Speed Crystal (HS) frequency range in
Section 9.1.1 “System Clock sources”.
Updated the device operating speed to up to 50 MHz in Section 9.1.2
“System Clock Selection”.
Updated Section 9.1.3 “PLL Configuration” to reflect the new
operating range/speed of 50 MIPS/50 MHz.
Updated Section 9.2 “Auxiliary Clock Generation”.
Section 22.0 “High-Speed, 10-Bit Analog-
to-Digital Converter (ADC)”
Updated the ADC Block Diagram for dsPIC33FJ32GS406 and
dsPIC33FJ64GS406 Devices with one SAR (see Ta b l e 2 2- 1).
Added Note 2 to ADCPC6: ADC Convert Pair Control Register 6 (see
Register 22-12).