Datasheet

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS70591E-page 332  2009-2012 Microchip Technology Inc.
REGISTER 22-10: ADCPC4: ADC CONVERT PAIR CONTROL REGISTER 4
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN9 PEND9 SWTRG9 TRGSRC9<4:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN8 PEND8 SWTRG8
TRGSRC8<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 IRQEN9: Interrupt Request Enable 9 bit
1 = Enable IRQ generation when requested conversion of channels AN19 and AN18 is completed
0 = IRQ is not generated
bit 14 PEND9: Pending Conversion Status 9 bit
1 = Conversion of channels AN19 and AN18 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 13 SWTRG9: Software Trigger 9 bit
1 = Start conversion of AN19 and AN18 (if selected in TRGSRC bits)
(1)
This bit is automatically cleared by hardware when the PEND9 bit is set.
0 = Conversion is not started
Note 1: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.