Datasheet

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS70591E-page 190  2009-2012 Microchip Technology Inc.
9.1.3 PLL CONFIGURATION
The primary oscillator and internal FRC oscillator can
optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides significant flexibility in
selecting the device operating speed. A block diagram
of the PLL is shown in Figure 9-2.
The output of the primary oscillator or FRC, denoted as
‘F
IN’, is divided down by a prescale factor (N1) of 2, 3,
... or 33 before being provided to the PLL’s Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected in the range of 0.8 MHz to 8 MHz. The
prescale factor ‘N1’ is selected using the
PLLPRE<4:0> bits (CLKDIV<4:0>).
The PLL Feedback Divisor, selected using the
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor, ‘M’,
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
frequency is in the range of 100 MHz to 200 MHz.
The VCO output is further divided by a postscale factor,
‘N2’. This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and
must be selected such that the PLL output frequency
(F
OSC) is in the range of 12.5 MHz to 100 MHz, which
generates device operating speeds of 6.25-50 MIPS.
For a primary oscillator or FRC oscillator, output ‘FIN’,
the PLL output ‘F
OSC’ is given by Equation 9-2.
EQUATION 9-2: FOSC CALCULATION
For example, suppose a 10 MHz crystal is being used
with the selected oscillator mode of XT with PLL (see
Equation 9-3).
• If PLLPRE<4:0> = 0000, then N1 = 2. This yields
a VCO input of 10/2 = 5 MHz, which is within the
acceptable range of 0.8-8 MHz.
• If PLLDIV<8:0> = 0x26, then M = 40. This yields a
VCO output of 5 x 40 = 200 MHz, which is within
the 100-200 MHz ranged needed.
• If PLLPOST<1:0> = 00, then N2 = 2. This pro-
vides a F
OSC of 200/2 = 100 MHz. The resultant
device operating speed is 100/2 = 40 MIPS.
EQUATION 9-3: XT WITH PLL MODE
EXAMPLE
FIGURE 9-2: PLL BLOCK DIAGRAM
(
)
M
N1 * N2
FOSC = FIN *
FCY =
FOSC
2
==
1
2
(
10000000 * 40
2 * 2
)
50 MIPS
0.8-8.0 MHz
Here
(1)
100-200 MHz
Here
(1)
Divide by
2, 4, 8
Divide by
2-513
Divide by
2-33
Source (Crystal, External Clock
PLLPRE
X
VCO
PLLDIV
PLLPOST
or Internal RC)
12.5-100 MHz
Here
(1,2)
FOSC
Note 1: This frequency range must be met at all times.
2: This frequency range is not supported for all devices.
N1
M
N2
F
VCO