Datasheet
2009-2012 Microchip Technology Inc. DS70591E-page 261
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
18.0 SERIAL PERIPHERAL
INTERFACE (SPI)
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices can be serial EEPROMs, shift
registers, display drivers, Analog-to-Digital Converters
and so on. The SPI module is compatible with SPI and
SIOP from Motorola
®
.
The SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buffer register, SPIxBUF. A control register,
SPIxCON, configures the module. Additionally, a status
register, SPIxSTAT, indicates status conditions.
The serial interface consists of these four pins:
• SDIx (Serial Data Input)
• SDOx (Serial Data Output)
• SCKx (Shift Clock Input Or Output)
• SSx
(Active-Low Slave Select)
In Master mode operation, SCK is a clock output; in
Slave mode, it is a clock input.
FIGURE 18-1: SPI MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/
610 and dsPIC33FJ64GS406/606/608/
610 families of devices. It is not intended
to be a comprehensive reference
source. To complement the information
in this data sheet, refer to Section 18.
“Serial Peripheral Interface (SPI)”
(DS70206) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Internal Data Bus
SDIx
SDOx
SSx
(1)
SCKx
bit 0
Shift Control
F
CY
Primary
1:1/4/16/64
Enable
Prescaler
Sync
SPIxBUF
Control
TransferTransfer
Write SPIxBUFRead SPIxBUF
16
SPIxCON1<1:0>
SPIxCON1<4:2>
Master Clock
Clock
Control
Secondary
Prescaler
1:1 to 1:8
SPIxRXB SPIxTXB
Note 1: The SPI1 module can be connected to the SS1
or ASS1 pins, which are controlled by clearing or setting the
ALTSS1 bit in the FPOR Configuration register. See Section 24.0 “Special Features” for more information.
SPIxSR
Edge
Select