Datasheet

 2009-2012 Microchip Technology Inc. DS70591E-page 249
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
bit 3-2 CLDAT<1:0>: State for PWMxH and PWMxL Pins if CLMOD is Enabled bits
(2)
IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode:
If current-limit is active, then CLDAT<1> provides the state for PWMxH.
If current-limit is active, then CLDAT<0> provides the state for PWMxL.
IFLTMOD (FCLCONx<15>) =
1: Independent Fault mode:
CLDAT<1:0> is ignored.
bit 1 SWAP: SWAP PWMxH and PWMxL Pins bit
1 = PWMxH output signal is connected to the PWMxL pin; PWMxL output signal is connected to the
PWMxH pin
0 = PWMxH and PWMxL pins are mapped to their respective pins
bit 0 OSYNC: Output Override Synchronization bit
1 = Output overrides, via the OVRDAT<1:0> bits, are synchronized to the PWM time base
0 = Output overrides, via the OVDDAT<1:0> bits, occur on next CPU clock boundary
REGISTER 16-19: IOCONx: PWM I/O CONTROL x REGISTER (CONTINUED)
Note 1: These bits should not be changed after the PWM module is enabled (PTEN = 1).
2: State represents the active/inactive state of the PWM depending on the POLH and POLL bit settings.
REGISTER 16-20: TRIGx: PWM PRIMARY TRIGGER x COMPARE VALUE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TRGCMP<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
TRGCMP<7:3> — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 TRGCMP<15:3>: Trigger Compare Value bits
When the primary PWM functions in the local time base, this register contains the compare values
that can trigger the ADC module.
bit 2-0 Unimplemented: Read as ‘0’