dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 16-Bit Digital Signal Controllers with High-Speed PWM, ADC and Comparators Operating Conditions Timers/Output Compare/Input Capture • 3.0V to 3.6V, -40ºC to +85ºC, DC to 50 MIPS • 3.0V to 3.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 PRODUCT FAMILIES The device names, pin counts, memory sizes, and peripheral availability of each device are listed in Table 1. The following pages show their pinout diagrams.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 RF1 SYNCI4/RF0 VDD VCAP PWM5H/UPDN1/CN16/RD7 PWM5L/CN15/RD6 PWM6H/CN14/RD5 PWM6L/CN13/RD4 OC4/SYNCO1/RD3 OC3/FLT7/RD2 OC2/SYNCO2/FLT6/RD1 = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ32GS406 dsPIC33FJ64GS406 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) = Pins are up to 5V tolerant PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 RF1 SYNCI4/RF0 VDD VCAP PWM5H/UPDN1/CN16/RD7 PWM5L/CN15/RD6 PWM6H/CN14/RD5 PWM6L/CN13/RD4 OC4/SYNCO1/RD3 OC3/FLT7/RD2 OC2/SYNCO2/FLT6/RD1 64-Pin QFN 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/SYNCI2/CN11/RG9 VSS VDD AN5/AQEB1/CN7/RB5 AN4
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 RF1 SYNCI4/RF0 VDD VCAP PWM5H/UPDN1/CN16/RD7 PWM5L/CN15/RD6 PWM6H/CN14/RD5 PWM6L/CN13/RD4 OC4/SYNCO1/FLT8/RD3 OC3/FLT7/RD2 OC2/SYNCO2/FLT6/RD1 = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ32GS606 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 C1TX/RF1 C1RX/SYNCI4/RF0 VDD VCAP PWM5H/UPDN1/CN16/RD7 PWM5L/CN15/RD6 PWM6H/CN14/RD5 PWM6L/CN13/RD4 OC4/SYNCO1/FLT8/RD3 OC3/FLT7/RD2 OC2/SYNCO2/FLT6/RD1 = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ64GS606 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/R
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) = Pins are up to 5V tolerant PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 RF1 SYNCI4/RF0 VDD VCAP PWM5H/UPDN1/CN16/RD7 PWM5L/CN15/RD6 PWM6H/CN14/RD5 PWM6L/CN13/RD4 OC4/SYNCO1/FLT8/RD3 OC3/FLT7/RD2 OC2/SYNCO2/FLT6/RD1 64-Pin QFN 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/SYNCI2/T5CK/CN11/RG9 VSS VDD AN5/CMP3B/
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) = Pins are up to 5V tolerant PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 C1TX/RF1 C1RX/SYNCI4/RF0 VDD VCAP PWM5H/UPDN1/CN16/RD7 PWM5L/CN15/RD6 PWM6H/CN14/RD5 PWM6L/CN13/RD4 OC4/SYNCO1/FLT8/RD3 OC3/FLT7/RD2 OC2/SYNCO2/FLT6/RD1 64-Pin QFN 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/SYNCI2/T5CK/CN11/RG9 VSS VDD
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) = Pins are up to 5V tolerant QEA2/RD12 PWM7H/OC4/SYNCO1/FLT8/RD3 OC3/FLT7/RD2 OC2/SYNCO2/FLT6/RD1 PWM6H/CN14/RD5 PWM6L/CN13/RD4 PWM7L/CN19/RD13 PWM5L/CN15/RD6 INDX2/SYNCI4/RG0 QEB2/RG1 C1TX/RF1 C1RX/RF0 VDD VCAP PWM5H/UPDN1/CN16/RD7 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 PWM2H/RE3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PWM3L/RE4 80-Pin TQFP PWM3H/RE5 PWM4L/RE6 1 60 2 59 PWM4H/RE7 AN16/T2CK/RC1 A
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) = Pins are up to 5V tolerant QEA2/RD12 PWM7H/OC4/SYNCO1/FLT8/RD3 OC3/FLT7/RD2 OC2/SYNCO2/FLT6/RD1 PWM6H/CN14/RD5 PWM6L/CN13/RD4 PWM7L/CN19/RD13 PWM5L/CN15/RD6 INDX2/SYNCI4/RG0 QEB2/RG1 C1TX/RF1 C1RX/RF0 VDD VCAP PWM5H/UPDN1/CN16/RD7 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 PWM2H/RE3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PWM3L/RE4 80-Pin TQFP PWM3H/RE5 PWM4L/RE6 1 60 2 59 PWM4H/RE7 AN16/T2CK/RC1 A
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) = Pins are up to 5V tolerant 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM9H/RG13 PWM9L/RG12 SYNCO1/FLT23/RG14 PWM1H/RE1 PWM1L/RE0 AN23/CN23/RA7 AN22/CN22/RA6 INDX2/RG0 QEB2/RG1 C1TX/RF1 C1RX/RF0 VDD VCAP PWM5H/UPDN1/CN16/RD7 PWM5L/CN15/RD6 PWM6H/CN14/RD5 PWM6L/CN13/RD4 PWM7L/CN19/RD13 QEA2/RD12 PWM7H/OC4/FLT8/RD3 OC3/FLT7/RD2 OC2/SYNCO2/FLT6/RD1 100-Pin T
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) = Pins are up to 5V tolerant 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM9H/RG13 PWM9L/RG12 SYNCO1/FLT23/RG14 PWM1H/RE1 PWM1L/RE0 AN23/CN23/RA7 AN22/CN22/RA6 INDX2/RG0 QEB2/RG1 C1TX/RF1 C1RX/RF0 VDD VCAP PWM5H/UPDN1/CN16/RD7 PWM5L/CN15/RD6 PWM6H/CN14/RD5 PWM6L/CN13/RD4 PWM7L/CN19/RD13 QEA2/RD12 PWM7H/OC4/FLT8/RD3 OC3/FLT7/RD2 OC2/SYNCO2/FLT6/RD1 100-Pin T
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Table of Contents dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Product Families ............................................................... 2 1.0 Device Overview ........................................................................................................................................................................ 17 2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers......................
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33F/PIC24H Family Reference Manual”. These documents should be considered as the primary reference for the operation of a particular module or device feature. Note 1: To access the documents listed below, browse to the documentation section of the dsPIC33FJ64GS610 product page of the Microchip web site (www.microchip.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70591E-page 16 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 1.0 Note: DEVICE OVERVIEW This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the latest sections in the “dsPIC33F/PIC24H Family Reference Manual”, which are available from the Microchip web site (www.microchip.com).
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 1-1: DEVICE BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller 16 8 PORTA DMA RAM 16 16 16 Data Latch Data Latch PCU PCH PCL Program Counter X RAM Y RAM Loop Control Logic Address Latch Address Latch 16 23 23 Stack Control Logic PORTB DMA Controller 16 23 16 16 16 PORTC Address Generator Units Address Latch Program Memory EA MUX Data Latch 24 Instruction Reg Control
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Name Pin Type Buffer Type AN0-AN23 I CLKI CLKO I O ST/CMOS External clock source input. Always associated with OSC1 pin function. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. OSC1 I OSC2 I/O ST/CMOS Oscillator crystal input.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX I O I O I O I O ST — ST — ST — ST — UART1 Clear-to-Send. UART1 Ready-to-Send. UART1 receive. UART1 transmit. UART2 Clear-to-Send. UART2 Ready-to-Send. UART2 receive. UART2 transmit. SCK1 SDI1 SDO1 SS1, ASS1 SCK2 SDI2 SDO2 SS2 I/O I O I/O I/O I O I/O ST ST — ST ST ST — ST Synchronous serial clock input/output for SPI1.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type FLT1-FLT23 SYNCI1-SYNCI4 SYNCO1-SYNCO2 PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H PWM4L PWM4H PWM5L PWM5H PWM6L PWM6H PWM7L PWM7H PWM8L PWM8H PWM9L PWM9H I I O O O O O O O O O O O O O O O O O O O ST ST — — — — — — — — — — — — — — — — — — — Fault inputs to PWM module. External synchronization signal to PWM master time base. PWM master time base for external device synchronization.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70591E-page 22 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic R R1 2.4 VSS VCAP VDD VDD 10 µF Tantalum • Device Reset • Device programming and debugging C dsPIC33F VSS VDD VSS VDD AVSS VDD AVDD VSS 0.1 µF Ceramic 0.1 µF Ceramic 0.1 µF Ceramic L1(1) Note 1: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and AVDD to improve ADC noise rejection.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 2.7 Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 MHz < FIN < 8 MHz to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start-up in the FRC mode first.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 2-4: DIGITAL PFC IPFC VHV_BUS |VAC| k1 k3 VAC ADC Channel k2 FET Driver ADC Channel PWM Output ADC Channel dsPIC33FJ32GS406 FIGURE 2-5: BOOST CONVERTER IMPLEMENTATION IPFC VINPUT VOUTPUT k1 k3 ADC Channel k2 FET Driver ADC Channel PWM Output ADC Channel dsPIC33FJ32GS406 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 2-6: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input 5V Output I5V PWM ADC Channel PWM FET Driver k7 k1 k2 Analog Comp. ADC Channel dsPIC33FJ32GS606 FIGURE 2-7: MULTI-PHASE SYNCHRONOUS BUCK CONVERTER 3.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 2-8: OFF-LINE UPS VDC Push-Pull Converter Full-Bridge Inverter VOUT+ VBAT + VOUTGND GND FET Driver FET Driver PWM PWM k2 k1 ADC ADC or Analog Comp. k3 FET Driver FET Driver FET Driver FET Driver PWM PWM PWM PWM dsPIC33FJ64GS610 ADC k4 k5 ADC ADC ADC PWM FET Driver k6 + Battery Charger 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 2-9: INTERLEAVED PFC VOUT+ |VAC| k4 VAC k3 k2 k1 VOUTFET Driver ADC Channel ADC Channel DS70591E-page 30 PWM FET Driver ADC Channel PWM ADC Channel ADC Channel dsPIC33FJ32GS608 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 2-10: PHASE-SHIFTED FULL-BRIDGE CONVERTER VIN+ Gate 6 Gate 3 Gate 1 VOUT+ S1 S3 VOUT- Gate 2 Gate 4 Gate 5 Gate 6 Gate 5 VIN- FET Driver k2 PWM ADC Channel k1 Analog Ground Gate 1 S1 FET Driver PWM Gate 3 S3 FET Driver ADC Channel dsPIC33FJ32GS606 PWM Gate 2 Gate 4 2009-2012 Microchip Technology Inc.
AC-TO-DC POWER SUPPLY WITH PFC AND THREE OUTPUTS (12V, 5V, AND 3.3V) ZVT with Current Doubler Synchronous Rectifier VHV_BUS Isolation Barrier VOUT IZVT 3.3V Multi-Phase Buck Stage 3.3V Output 12V Input I3.3V_1 FET Driver FET Driver k4 FET Driver 5V Output 5V Buck Stage I3.3V_2 ADC ADC Channel Channel PWM Output ADC Ch. UART RX ADC Channel FET Driver k6 k7 Analog Comp. ADC Channel Secondary Controller dsPIC33FJ64GS610 PFC Stage k2 UART TX FET Driver FET Driver I3.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 3.0 CPU Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS70204) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 3.3 Special MCU Features The dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 supports 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 3-2: PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 3.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 3-2: U-0 — bit 15 U-0 — R/W-0 SATB Legend: R = Readable bit -n = Value at POR bit 11 bit 10-8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: U-0 — R/W-0 US R/W-0 EDT(1) R-0 R-0 DL<2:0> R-0 bit 8 R/W-0 SATA bit 7 bit 15-13 bit 12 CORCON: CORE CONTROL REGISTER R/W-1 SATDW R/W-0 ACCSAT C = Clearable bit W = Writable bit ‘1’ = Bit is set R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 U = Unimpleme
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 3.5 Arithmetic Logic Unit (ALU) The dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 S a 40 Round t 16 u Logic r a t e 40-Bit Accumulator A 40-Bit Accumulator B Carry/Borrow Out Carry/Borrow In Saturate Adder Negate 40 40 40 16 X Data Bus Barrel Shifter 40 Y Data Bus Sign-Extend 32 Zero Backfill 16 32 33 17-Bit Multiplier/Scaler 16 16 To/From W Array DS70591E-page 40 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 3.6.1 MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled).
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 3.6.3.2 Data Space Write Saturation 3.6.4 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70591E-page 44 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the dsPIC33F/PIC24H Family Reference Manual, “Section 4. Program Memory” (DS70203), which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 All dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.2 Data Address Space The CPU has a separate 16-bit-wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 4-3: DATA MEMORY MAP FOR DEVICES WITH 4-KBYTE RAM MSB Address MSb 2-Kbyte SFR Space LSb 0x0000 0x0001 SFR Space 0x07FF 0x0801 0x0FFF 0x1001 X Data RAM (X) Y Data RAM (Y) 0x07FE 0x0800 0x0FFE 0x1000 0x17FF 0x1801 0x17FE 0x1800 0x8001 0x8000 6-Kbyte Near Data Space X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70591E-page 48 LSB Address 16 Bits 0xFFFE 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 4-4: DATA MEMORY MAP FOR DEVICES WITH 8-KBYTE RAM MSB Address MSb 2-Kbyte SFR Space LSB Address 16 Bits LSb 0x0000 0x0001 SFR Space 0x07FF 0x0801 X Data RAM (X) 0x17FF 0x1801 0x07FE 0x0800 0x17FE 0x1800 8-Kbyte Near Data Space Y Data RAM (Y) 0x1FFF 0x2001 0x1FFE 0x27FF 0x2801 0x27FE 0x2800 0x8001 0x8000 0x2000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 4-5: DATA MEMORY MAP FOR DEVICES WITH 9-KBYTE RAM MSB Address MSb 2-Kbyte SFR Space LSB Address 16 Bits LSb 0x0000 0x0001 SFR Space 0x07FF 0x0801 X Data RAM (X) 0x17FF 0x1801 0x07FE 0x0800 0x17FE 0x1800 8-Kbyte Near Data Space Y Data RAM (Y) 0x1FFF 0x2001 0x1FFE 0x27FF 0x2801 0x27FE 0x2800 0x2BFF 0x2C01 0x2000 DMA RAM 0x2BFE 0x2C00 0x8001 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70591E-
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.2.5 X AND Y DATA SPACES The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths.
SFR Name SFR Addr.
SFR Name SFR Addr.
File Name CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32GS608/610 AND dsPIC33FJ64GS608/610 DEVICES SFR Addr.
File Name SFR Addr.
File Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS610 DEVICES (CONTINUED) SFR Addr.
SFR Name SFR Addr.
SFR Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES (CONTINUED) SFR Addr.
SFR Name SFR Addr.
SFR Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS606 DEVICES (CONTINUED) SFR Addr.
SFR Name SFR Addr.
SFR Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES (CONTINUED) SFR Addr.
SFR Name SFR Addr.
SFR Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS610 DEVICES (CONTINUED) SFR Addr.
SFR Name SFR Addr.
SFR Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS608 (CONTINUED) SFR Addr.
SFR Name SFR Addr.
SFR Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS606 DEVICES (CONTINUED) SFR Addr.
SFR Name SFR Addr.
SFR Name SFR Addr.
File Name HIGH-SPEED PWM REGISTER MAP SFR Addr.
HIGH-SPEED PWM GENERATOR 2 REGISTER MAP File Name SFR Addr.
File Name HIGH-SPEED PWM GENERATOR 3 REGISTER MAP SFR Addr.
HIGH-SPEED PWM GENERATOR 4 REGISTER MAP File Name SFR Addr.
HIGH-SPEED PWM GENERATOR 5 REGISTER MAP SFR Addr.
HIGH-SPEED PWM GENERATOR 6 REGISTER MAP SFR Addr.
File Name HIGH-SPEED PWM GENERATOR 7 REGISTER MAP (EXCLUDES dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES) SFR Addr.
HIGH-SPEED PWM GENERATOR 8 REGISTER MAP (EXCLUDES dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES) File Name SFR Addr.
HIGH-SPEED PWM GENERATOR 9 REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES File Name SFR Addr.
I2C2 REGISTER MAP SFR Addr.
SPI1 REGISTER MAP File Name SFR Addr.
File Name SFR Addr.
File Name SFR Addr. HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES ONLY (CONTINUED) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets ADCBUF22 036C ADC Data Buffer 22 xxxx ADCBUF23 036E ADC Data Buffer 23 xxxx ADCBUF24 0370 ADC Data Buffer 24 xxxx ADCBUF25 0372 ADC Data Buffer 25 xxxx Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’.
SFR File Name Addr.
HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS606 AND dsPIC33FJ64GS606 DEVICES SFR Addr.
File Name HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES SFR Addr.
File Name SFR Addr.
ECAN1 REGISTER MAP WHEN WIN (C1CTRL1<0>) = 0 OR 1 SFR Addr.
File Name SFR Addr.
File Name SFR Addr. ECAN1 REGISTER MAP WHEN WIN (C1CTRL1<0>) = 1 (CONTINUED) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 C1RXF11EID 066E EID<15:8> C1RXF12SID 0670 SID<10:3> C1RXF12EID 0672 EID<15:8> C1RXF13SID 0674 SID<10:3> C1RXF13EID 0676 EID<15:8> C1RXF14SID 0678 SID<10:3> C1RXF14EID 067A EID<15:8> C1RXF15SID 067C SID<10:3> C1RXF15EID 067E EID<15:8> Legend: Bit 10 Bit 9 Bit 8 Bit 7 x = unknown value on Reset, — = unimplemented, read as ‘0’.
ANALOG COMPARATOR CONTROL REGISTER MAP SFR Addr.
File Name PORTB REGISTER MAP SFR Addr.
File Name PORTD REGISTER MAP FOR dsPIC33FJ32GS608/610 AND dsPIC33FJ64GS608/610 DEVICES SFR Addr.
File Name PORTF REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES SFR Addr.
File Name PORTG REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES SFR Addr.
NVM REGISTER MAP File Name SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 NVMCON 0760 WR WREN WRERR — — — — — — ERASE — NVMKEY 0766 — — — — — — — — Legend: Note 1: Bit 3 — Bit 2 Bit 1 Bit 0 All Resets 0000(1) NVMOP<3:0> NVMKEY<7:0> 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset value shown is for POR only.
File Name PMD REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES SFR Addr.
File Name PMD REGISTER MAP FOR dsPIC33FJ32GS606 DEVICES SFR Addr.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.2.7 4.3 SOFTWARE STACK In addition to its use as a working register, the W15 register in the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices is also used as a Software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 4-6.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 4-66: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode File Register Direct Description The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the Effective Address (EA). Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.4 Modulo Addressing 4.4.1 Modulo Addressing mode is a method used to provide an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms. Modulo Addressing can operate in either data or program space (since the Data Pointer mechanism is essentially the same for both).
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.4.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 4-8: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-67: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.6 Interfacing Program and Data Memory Spaces 4.6.1 Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. The dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 architecture uses a 24-bit-wide program space and a 16-bit-wide data space.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) Program Counter 0 0 23 Bits EA Table Operations(2) 1/0 1/0 TBLPAG 8 Bits 16 Bits 24 Bits Select Program Space Visibility(1) (Remapping) 0 1 EA 0 PSVPAG 8 Bits 15 Bits 23 Bits User/Configuration Space Select Byte Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in th
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.6.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.6.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL/H).
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70591E-page 108 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 5.0 FLASH PROGRAM MEMORY PGED3), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the Digital Signal Controller (DSC) just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 5.2 RTSP Operation The dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. Table 27-12 shows typical erase and programming times.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 U-0 R/W-0(1) U-0 U-0 — ERASE — — R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) NVMOP<3:0>(2) bit 7 bit 0 Legend: SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register bits (write-only) DS70591E-page 112
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 5.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. One row of program Flash memory can be programmed at a time. To achieve this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word M
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 6.0 RESETS A simplified block diagram of the Reset module is shown in Figure 6-1. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 RCON: RESET CONTROL REGISTER(1) REGISTER 6-1: R/W-0 TRAPR bit 15 R/W-0 IOPUWR U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 VREGS bit 8 R/W-0 EXTR bit 7 R/W-0 SWR R/W-0 SWDTEN(2) R/W-0 WDTO R/W-0 SLEEP R/W-0 IDLE R/W-1 BOR R/W-1 POR bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-9 bit 8 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown TRAPR: Trap Reset
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 6.1 System Reset The dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices have two types of Reset: • Cold Reset • Warm Reset A Cold Reset is the result of a Power-on Reset (POR) or a Brown-out Reset (BOR). On a Cold Reset, the FNOSCx Configuration bits in the FOSC Configuration register select the device clock source.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 6-2: SYSTEM RESET TIMING VBOR VPOR VDD TPOR POR BOR 1 TBOR 2 3 TPWRT SYSRST 4 Oscillator Clock TOSCD TOST TLOCK 6 TFSCM FSCM 5 Device Status Reset Run Time Note 1: POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 6.2 Power-on Reset (POR) A Power-on Reset (POR) circuit ensures the device is reset from power-on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed. The delay, TPOR, ensures the internal device bias circuits become stable. The device supply voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the POR. Refer to Section 27.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 6.4 External Reset (EXTR) The External Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt Trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse width will generate a Reset. Refer to Section 27.0 “Electrical Characteristics” for minimum pulse width specifications. The External Reset (MCLR) pin (EXTR) bit in the Reset Control (RCON) register is set to indicate the MCLR Reset.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 6.9 Using the RCON Status Bits The user application can read the Reset Control (RCON) register after any device Reset to determine the cause of the Reset. Note: Table 6-2 provides a summary of the Reset flag bit operation. The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70591E-page 122 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 7.0 INTERRUPT CONTROLLER Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 47. “Interrupts (Part V)” (DS70597) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Decreasing Natural Order Priority FIGURE 7-1: Note 1: DS70591E-page 124 dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrup
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 7-1: INTERRUPT VECTORS Vector Number Interrupt Request (IQR) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29-31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21-23 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47-56 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39-48 57 58 59-60 49 50 51-52 61 62 53 54 IVT Address AIVT Address Interrupt Source Highest Natural Order Priority 0x000014 0x000114 INT0 – Extern
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 7-1: INTERRUPT VECTORS (CONTINUED) Vector Number Interrupt Request (IQR) 63-64 55-56 65 66 67-72 57 58 59-64 73 74 75-77 65 66 67-69 78 79 80 81 82 83 84-88 70 71 72 73 74 75 76-80 89 90 91 92 93 94-101 81 82 83 84 85 86-93 102 103 104 105 106 107 108 109 110 111 112 113 114-117 94 95 96 97 98 99 100 101 102 103 104 105 106-109 118 119 120 121 122 123 124 125 110 111 112 113 114 115 116 117 DS70591E-page 126 IVT Address
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 7.3 Interrupt Control and Status Registers The dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices implement 44 registers for the interrupt controller: • • • • • • INTCON1 INTCON2 IFSx IECx IPCx INTTREG 7.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 SR: CPU STATUS REGISTER(1) REGISTER 7-1: R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R-0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2(2) IPL1(2) IPL0(2) RA N OV Z C bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown IPL<2:0>: C
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit i
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IF ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = B
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt req
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-6: R/W-0 U2TXIF bit 15 U-0 — IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 U2RXIF R/W-0 INT2IF R/W-0 T5IF R/W-0 T4IF R/W-0 OC4IF R/W-0 OC3IF R/W-0 DMA2IF bit 8 U-0 — U-0 — R/W-0 INT1IF R/W-0 CNIF R/W-0 AC1IF R/W-0 MI2C1IF R/W-0 SI2C1IF bit 0 bit 7 Legend: R = Readable bit -n = Value at POR bit 12 bit 11 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7-5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit ‘1’ = Bit is
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC4IF IC3IF DMA3IF C1IF(1) C1RXIF(1) SPI2IF SPI2EIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Re
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — QEI1IF PSEMIF — bit 15 bit 8 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 — INT4IF INT3IF — — MI2C2IF SI2C2IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10 QEI1IF:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 U-0 R/W-0 U-0 R/W-0 U-0 — — — — QEI2IF — PSESMIF — bit 15 bit 8 U-0 R/W-0 — C1TXIF (1) U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — U2EIF U1EIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ b
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 PWM2IF PWM1IF ADCP12IF — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — ADCP11IF ADCP10IF ADCP9IF ADCP8IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWM2IF: PWM2
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-11: IFS6: INTERRUPT FLAG STATUS REGISTER 6 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 ADCP1IF ADCP0IF — — — — AC4IF AC3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AC2IF PWM9IF PWM8IF PWM7IF PWM6IF PWM5IF PWM4IF PWM3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADCP1IF
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-12: IFS7: INTERRUPT FLAG STATUS REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ADCP7IF ADCP6IF ADCP5IF ADCP4IF ADCP3IF ADCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5 ADCP7
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-13: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IE ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared b
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-13: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70591E-page 142
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-14: R/W-0 U2TXIE bit 15 U-0 — IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 U2RXIE R/W-0 INT2IE R/W-0 T5IE R/W-0 T4IE R/W-0 OC4IE R/W-0 OC3IE R/W-0 DMA2IE bit 8 U-0 — U-0 — R/W-0 INT1IE R/W-0 CNIE R/W-0 AC1IE R/W-0 MI2C1IE R/W-0 SI2C1IE bit 0 bit 7 Legend: R = Readable bit -n = Value at POR bit 12 bit 11 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7-5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit ‘1’ = B
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-15: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 — IC4IE R/W-0 IC3IE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMA3IE C1IE(1) C1RXIE(1) SPI2IE SPI2EIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-16: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — QEI1IE PSEMIE — bit 15 bit 8 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 — INT4IE INT3IE — — MI2C2IE SI2C2IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10 QEI1
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-17: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 R/W-0 U-0 R/W-0 U-0 — — — — QEI2IE — PSESMIE — bit 15 bit 8 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — C1TXIE(1) — — — U2EIE U1EIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-18: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 PWM2IE PWM1IE ADCP12IE — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 PWM2IE: PWM2 Interrupt Enable bit 1 = Interrupt request
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-19: IEC6: INTERRUPT ENABLE CONTROL REGISTER 6 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 ADCP1IE ADCP0IE — — — — AC4IE AC3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AC2IE — — — PWM6IE PWM5IE PWM4IE PWM3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADCP1IE: ADC Pair 1
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-20: IEC7: INTERRUPT ENABLE CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ADCP7IE ADCP6IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5 AD
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-21: U-0 IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 R/W-1 — R/W-0 R/W-0 T1IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC1IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 INT0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Ti
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-22: U-0 IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 R/W-1 — R/W-0 R/W-0 T2IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC2IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC2IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 DMA0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-23: U-0 IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 R/W-1 — R/W-0 R/W-0 U1RXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 SPI1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 SPI1EIP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 T3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-24: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 DMA1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 ADIP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 U1TXIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-25: U-0 IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 R/W-1 — R/W-0 R/W-0 CNIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 AC1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 MI2C1IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 SI2C1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-26: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 INT1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Pr
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-27: U-0 IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 R/W-1 — R/W-0 R/W-0 T4IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC4IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 OC3IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 DMA2IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-28: U-0 IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 R/W-1 — R/W-0 R/W-0 U2TXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 U2RXIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 INT2IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 T5IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP<2:0>:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-29: U-0 IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 R/W-1 R/W-0 R/W-0 C1IP<2:0>(1) — U-0 R/W-1 R/W-0 R/W-0 C1RXIP<2:0>(1) — bit 15 bit 8 U-0 R/W-1 — R/W-0 SPI2IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 SPI2EIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-30: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 IC4IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC3IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 DMA3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-31: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 MI2C2IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 SI2C2IP<2:0> R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 MI2C2IP<2:0>: I2C2 Ma
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-32: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 INT4IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 INT3IP<2:0> R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 INT4IP<2:0>: External I
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-33: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 QEI1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 PSEMIP<2:0> R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 QEI1IP<2:0>: QEI1 Inter
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-34: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 U2EIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 U1EIP<2:0> R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 U2EIP<2:0>: UART2 Error I
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-35: IPC17: INTERRUPT PRIORITY CONTROL REGISTER 17 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 C1TXIP<2:0>(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 C1TXIP<2:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-36: U-0 IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 R/W-1 — R/W-0 R/W-0 QEI2IP<2:0> U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 PSESMIP<2:0> R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 QEI2IP
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-37: U-0 IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 R/W-1 — R/W-0 R/W-0 ADCP10IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 ADCP9IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 ADCP8IP<2:0> R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-38: IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 ADCP12IP<2:0> R/W-0 U-0 R/W-1 R/W-0 R/W-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ADCP12IP<2:0>: ADC Pair 12
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-39: U-0 IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23 R/W-1 — R/W-0 R/W-0 U-0 PWM2IP<2:0> R/W-1 — R/W-0 R/W-0 PWM1IP<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 PWM2IP<2:0>: PWM2 Interrup
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-40: U-0 IPC24: INTERRUPT PRIORITY CONTROL REGISTER 24 R/W-1 — R/W-0 R/W-0 U-0 PWM6IP<2:0> R/W-1 — R/W-0 R/W-0 PWM5IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 R/W-0 U-0 PWM4IP<2:0> — R/W-1 R/W-0 R/W-0 PWM3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 PWM6IP
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-41: U-0 IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25 R/W-1 — R/W-0 R/W-0 U-0 AC2IP<2:0> R/W-1 — R/W-0 R/W-0 PWM9IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 R/W-0 U-0 PWM8IP<2:0> — R/W-1 R/W-0 R/W-0 PWM7IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 AC2IP<2
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-42: IPC26: INTERRUPT PRIORITY CONTROL REGISTER 26 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 AC4IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 AC3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AC4IP<2:0>: Analog Comparato
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-43: U-0 IPC27: INTERRUPT PRIORITY CONTROL REGISTER 27 R/W-1 — R/W-0 R/W-0 ADCP1IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 ADCP0IP<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 ADCP
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-44: U-0 IPC28: INTERRUPT PRIORITY CONTROL REGISTER 28 R/W-1 — R/W-0 R/W-0 ADCP5IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 ADCP4IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 ADCP3IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 ADCP2IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 ADC
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-45: IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 ADCP7IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 ADCP6IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ADC
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-46: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 — — — — R-0 R-0 R-0 R-0 ILR<3:0> bit 15 bit 8 U-0 R-0 R-0 — R-0 R-0 R-0 R-0 R-0 VECNUM<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 111
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 7.4 Interrupt Setup Procedures 7.4.1 7.4.3 INITIALIZATION Complete the following steps to configure an interrupt source at initialization: 1. 2. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 8.0 DIRECT MEMORY ACCESS (DMA) Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 22. “Direct Memory Access (DMA)” (DS70182) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 8.1 The DMA Controller features four identical data transfer channels. Each channel has its own set of control and status registers. Each DMA Channel can be configured to copy data either from buffers stored in dual port DMA RAM to peripheral SFRs or from peripheral SFRs to buffers in DMA RAM.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 8-1: DMAxCON: DMA CHANNEL x CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CHEN SIZE DIR HALF NULLW — — — bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 AMODE<1:0> U-0 U-0 — — R/W-0 R/W-0 MODE<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CHEN: DMA Channel Enable b
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 8-2: DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 FORCE(1) — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRQSEL<6:0>(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FORCE: Force DMA Transfer bit(1) 1 = Forces a sing
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 8-4: R/W-0 DMAxSTB: DMA CHANNEL x RAM START ADDRESS OFFSET REGISTER B R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STB<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STB<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown STB<15:0>: Secondary DMA RAM Start Address bits
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 8-6: DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 CNT<9:8>(2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 CNT<9:0>: DMA Transfer Co
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 8-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0 U-0 U-0 U-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 — — — — PWCOL3 PWCOL2 PWCOL1 PWCOL0 bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 — — — — XWCOL3 XWCOL2 XWCOL1 XWCOL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bi
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 8-8: DMACS1: DMA CONTROLLER STATUS REGISTER 1 U-0 U-0 U-0 U-0 — — — — R-1 R-1 R-1 R-1 LSTCH<3:0> bit 15 bit 8 U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — PPST3 PPST2 PPST1 PPST0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 LSTCH<3:0>: Last DMA Channel Act
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 8-9: R-0 DSADR: MOST RECENT DMA RAM ADDRESS R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<15:8> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits 2009-2012 Microchip Tech
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70591E-page 186 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 9.0 OSCILLATOR CONFIGURATION Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 42. “Oscillator (Part IV)” (DS70307) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 OSC1 OSCILLATOR SYSTEM DIAGRAM Primary Oscillator (POSC) POSCCLK R(2) DOZE<2:0> XT, HS, EC XTPLL, HSPLL, ECPLL, FRCPLL S3 S1 POSCMD<1:0> FVCO(1) S1/S3 To ADC and Auxiliary Clock Generator FRC Oscillator FRCDIV OSC2 PLL(1) S2 DOZE FIGURE 9-1: TUN<5:0> ÷ 16 FCY(4) FP(4) FRCDIVN ÷2 S7 FOSC FRCDIV<2:0> FRCDIV16 FRC LPRC LPRC Oscillator Secondary Oscillator (SOSC) SOSC SOSCO S6 S0 S5 S4 LPOSCEN SOSCI Clock Fail Clock Swit
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 9.1 CPU Clocking System The dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices provide six system clock options: • • • • • • • Fast RC (FRC) Oscillator FRC Oscillator with PLL Primary (XT, HS, or EC) Oscillator Primary Oscillator with PLL Low-Power RC (LPRC) Oscillator FRC Oscillator with Postscaler Secondary (LP) Oscillator 9.1.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 9.1.3 PLL CONFIGURATION For a primary oscillator or FRC oscillator, output ‘FIN’, the PLL output ‘FOSC’ is given by Equation 9-2. The primary oscillator and internal FRC oscillator can optionally use an on-chip PLL to obtain higher speeds of operation. The PLL provides significant flexibility in selecting the device operating speed. A block diagram of the PLL is shown in Figure 9-2.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 9.2 Auxiliary Clock Generation The auxiliary clock generation is used for a peripherals that need to operate at a frequency unrelated to the system clock such as a PWM or ADC. The primary oscillator and internal FRC oscillator sources can be used with an auxiliary PLL to obtain the auxiliary clock. The auxiliary PLL has a fixed 16x multiplication factor. 9.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 9.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED) bit 3 CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2-1 Unimplemented: Read as ‘0’ bit 0 OSWEN: Oscillator Switch Enable bit 1 = Requests oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: 2: Writes to this register require an unlock sequ
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 9-2: R/W-0 CLKDIV: CLOCK DIVISOR REGISTER R/W-0 ROI R/W-1 R/W-1 R/W-0 R/W-0 DOZEN(1) DOZE<2:0> R/W-0 R/W-0 FRCDIV<2:0> bit 15 bit 8 R/W-0 R/W-1 PLLPOST<1:0> U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 PLLPRE<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 9-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PLLDIV8 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feed
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 9-4: OSCTUN: OSCILLATOR TUNING REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TUN<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 =
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 9-5: ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER R/W-0 R-0 R/W-1 U-0 U-0 ENAPLL APLLCK SELACLK — — R/W-1 R/W-1 R/W-1 APSTSCLR<2:0> bit 15 bit 0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ASRCSEL FRCSEL — — — — — — bit 7 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ENAPLL: Auxiliary PLL
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 9-6: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 ROON — ROSSLP ROSEL R/W-0 R/W-0 R/W-0 R/W-0 RODIV<3:0>(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ROON: Reference Oscillator Output Enable bit 1 = Refer
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 9.5 Clock Switching Operation Applications are free to switch among any of the four clock sources (primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, dsPIC33FJ32GS406/606/608/ 610 and dsPIC33FJ64GS406/606/608/610 devices have a safeguard lock built into the switch process. Note: 9.5.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70591E-page 200 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 10.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 10.2.2 IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 10.5 “Peripheral Module Disable”). • If the WDT or FSCM is enabled, the LPRC also remains active.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 10.5 Peripheral Module Disable The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled using the appropriate PMD control bit, the peripheral is in a minimum power consumption state.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD(1) — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 I2C1MD U2MD U1MD SPI2MD SPI1MD — C1MD ADCMD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED) bit 3 SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2 Unimplemented: Read as ‘0’ bit 1 C1MD: ECAN1 Module Disable bit 1 = ECAN1 module is disabled 0 = ECAN1 module is enabled bit 0 ADCMD: ADC Module Disable bit 1 = ADC module is disabled 0 = ADC module is enabled Note 1: Once the PWM module is re-enabled (PWMMD is
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — IC4MD IC3MD IC2MD IC1MD bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — OC4MD OC3MD OC2MD OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 — — — — — CMPMD — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 — — QEI2MD — — — I2C2MD — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10 CMPMD: Analog Compa
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 10-5: PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWM8MD PWM7MD PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 PWM8MD: PWM Generator
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 10-6: PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CMP4MD CMP3MD CMP2MD CMP1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PWM9MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11 CMP4
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70591E-page 210 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 11.0 I/O PORTS Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “I/O Ports” (DS70193) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module WR TRIS Output Enable 0 1 Output Data 0 Read TRIS Data Bus I/O 1 D Q I/O Pin CK TRIS Latch D WR LAT + WR PORT Q CK Data Latch Read LAT Input Data Read PORT DS70591E-page 212 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 11.2 Open-Drain Configuration In addition to the PORT, LAT and TRIS registers for data control, some digital-only port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70591E-page 214 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 12.0 TIMER1 The unique features of Timer1 allow it to be used for Real-Time Clock (RTC) applications. A block diagram of Timer1 is shown in Figure 12-1. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 11.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 R/W-0 TCKPS<1:0> U-0 R/W-0 R/W-0 U-0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 13.0 TIMER2/3/4/5 FEATURES Timer2 and Timer4 are Type B timers that offer the following major features: Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 11.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 The Timer2/3/4/5 modules can operate in one of the following modes: • Timer mode • Gated Timer mode • Synchronous Counter mode In Timer and Gated Timer modes, the input clock is derived from the internal instruction cycle clock (FCY). In Synchronous Counter mode, the input clock is derived from the external clock input at the TxCK pin.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 13-3: 32-BIT TIMER BLOCK DIAGRAM Gate Sync Falling Edge Detect 1 PRx Set TyIF Flag PRy 0 Equal Comparator Prescaler (/n) FCY 10 lsw 00 TCKPS<1:0> Prescaler (/n) TGATE Sync TMRx(1) msw TMRy(2) Reset x1 TxCK TCKPS<1:0> TGATE TMRyHLD TCS Data Bus <15:0> Note 1: Timerx is a Type B Timer (x = 2, 4). 2: Timery is a Type C Timer (y = 3, 5). 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 13-1: TxCON: TIMERx CONTROL REGISTER (x = 2, 4) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 R/W-0 TCKPS<1:0> R/W-0 U-0 R/W-0 U-0 T32 — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timerx On bit When T32 = 1 (in 32-Bit Timer mode
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 13-2: TyCON: TIMERy CONTROL REGISTER (y = 3, 5) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(2) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE(2) R/W-0 R/W-0 TCKPS<1:0>(2) U-0 U-0 R/W-0 U-0 — — TCS(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timery On bit(2) 1 = Starts 16-bit Ti
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70591E-page 222 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 14.0 INPUT CAPTURE Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. “Input Capture” (DS70198) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 14.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 15.0 OUTPUT COMPARE The output compare module can select either Timer2 or Timer3 for its time base. The module compares the value of the timer with the value of one or two Compare registers depending on the operating mode selected. The state of the output pin changes when the timer value matches the Compare register value.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 15.1 Output Compare Modes application must disable the associated timer when writing to the Output Compare Control registers to avoid malfunctions. Configure the Output Compare modes by setting the appropriate Output Compare Mode (OCM<2:0>) bits in the Output Compare Control (OCxCON<2:0>) register. Table 15-1 lists the different bit settings for the Output Compare modes. Figure 15-2 illustrates the output compare operation for various modes.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 15-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1, 2) U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — OCSIDL — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0, HC R/W-0 — — — OCFLT OCTSEL R/W-0 R/W-0 R/W-0 OCM<2:0> bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70591E-page 228 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 16.0 HIGH-SPEED PWM Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 43. “High-Speed PWM” (DS70323) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 16-1: HIGH-SPEED PWMx MODULE ARCHITECTURAL DIAGRAM SYNCIx Data Bus Primary and Secondary Master Time Base SYNCOx Synchronization Signal PWM1 Interrupt PWM1H PWM Generator 1 PWM1L Fault, Current-Limit and Dead-Time Compensation Synchronization Signal PWM2 Interrupt PWM2H PWM Generator 2 PWM2L Fault, Current-Limit and Dead-Time Compensation CPU PWM3 through PWM7 Synchronization Signal PWM8 Interrupt PWM8H PWM Generator 8 PWM8L Fault
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 16-2: SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF THE HIGH-SPEED PWMx PTCON, PTCON2 SYNCI1 Module Control and Timing STCON, STCON2 PTPER SEVTCMP Comparator Comparator SYNCI4 ••• SYNCO1 Special Event Compare Trigger Special Event Postscaler Special Event Trigger Master Time Base Counter Clock Prescaler PMTMR STPER SEVTCMP Comparator Comparator Primary Master Time Base SYNCO2 Special Event Compare Trigger Special Event Pos
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 16.3 Control Registers The following registers control the operation of the High-Speed PWM module.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-1: PTCON: PWM TIME BASE CONTROL REGISTER R/W-0 U-0 R/W-0 HS/HC-0 R/W-0 R/W-0 PTEN — PTSIDL SESTAT SEIEN EIPU(1) R/W-0 R/W-0 SYNCPOL(1) SYNCOEN(1) bit 15 bit 8 R/W-0 R/W-0 SYNCEN(1) R/W-0 R/W-0 R/W-0 R/W-0 SYNCSRC<2:0>(1) R/W-0 R/W-0 SEVTPS<3:0>(1) bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Val
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-1: bit 3-0 Note 1: PTCON: PWM TIME BASE CONTROL REGISTER (CONTINUED) SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits(1) 1111 = 1:16 Postscaler generates special event trigger on every sixteenth compare match event • • • 0001 = 1:2 Postscaler generates special event trigger on every second compare match event 0000 = 1:1 Postscaler generates special event trigger on every compare match event These bits should be
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-2: PTCON2: PWM CLOCK DIVIDER SELECT REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 PCLKDIV<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 PCLKDIV<2:0>
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-4: R/W-0 SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<7:3> U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 SEVTCMP<15:3>: Special Event Compare Count Value bits bit 2-0 Uni
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-5: STCON: PWM SECONDARY MASTER TIME BASE CONTROL REGISTER U-0 U-0 U-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — SESTAT SEIEN EIPU(1) SYNCPOL SYNCOEN bit 15 bit 8 R/W-0 R/W-0 SYNCEN R/W-0 R/W-0 R/W-0 SYNCSRC<2:0> R/W-0 R/W-0 R/W-0 SEVTPS<3:0> bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-6: STCON2: PWM SECONDARY CLOCK DIVIDER SELECT REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 PCLKDIV<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 PC
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-8: R/W-0 SSEVTCMP: PWM SECONDARY SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEVTCMP<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEVTCMP<7:3> U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 SSEVTCMP<15:3>: Special Event Compare Count Value bits b
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-10: MDC: PWM MASTER DUTY CYCLE REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MDC<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MDC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: 2: x = Bit is unknown MDC<15:0>: PWM Master Duty Cycle Value bits The small
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-11: PWMCONx: PWM CONTROL x REGISTER HS/HC-0 HS/HC-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTSTAT(1) CLSTAT(1) TRGSTAT FLTIEN CLIEN TRGIEN ITB(3) MDCS(3) bit 15 bit 8 R/W-0 R/W-0 DTC<1:0> R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 DTCP(4) — MTBS CAM(2,3,5) XPRES(6) IUE bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-11: PWMCONx: PWM CONTROL x REGISTER (CONTINUED) bit 7-6 DTC<1:0>: Dead-Time Control bits 11 = Dead-Time Compensation mode 10 = Dead-time function is disabled 01 = Negative dead time is actively applied for Complementary Output mode 00 = Positive dead time is actively applied for all output modes bit 5 DTCP: Dead-Time Compensation Polarity bit(4) 1 = If DTCMPx = 0, PWMxL is shortened and PWMxH is lengthened If DTCMPx = 1, PWMxH is s
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-12: PDCx: PWM GENERATOR DUTY CYCLE x REGISTER(1,2,3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: 2: 3: x = Bit is unknown PDCx<15:0>: PWM Generator # Duty Cycle
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-14: PHASEx: PWM PRIMARY PHASE SHIFT x REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: 2: x = Bit is unknown PHASEx<15:0>: PWM Phase Shift Value or
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-15: SPHASEx: PWM SECONDARY PHASE SHIFT x REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPHASEx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPHASEx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: 2: x = Bit is unknown SPHASEx<15:0>: Secondary Phase Off
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-16: DTRx: PWM DEAD-TIME x REGISTER U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTRx<13:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTRx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-0 DTRx<13:0>: Unsigned 14-Bit Va
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-18: TRGCONx: PWM TRIGGER CONTROL x REGISTER R/W-0 R/W-0 R/W-0 R/W-0 TRGDIV<3:0> U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 R/W-0 U-0 DTM(1) — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSTRT<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 TRGDIV<3:0>: Trigger # Output Divider bits
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 aa REGISTER 16-19: IOCONx: PWM I/O CONTROL x REGISTER R/W-0 R/W-0 PENH PENL R/W-0 POLH R/W-0 POLL R/W-0 R/W-0 PMOD<1:0>(1) R/W-0 R/W-0 OVRENH OVRENL bit 15 bit 8 R/W-0 R/W-0 OVRDAT<1:0> R/W-0 R/W-0 FLTDAT<1:0>(2) R/W-0 R/W-0 CLDAT<1:0>(2) R/W-0 R/W-0 SWAP OSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bi
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-19: IOCONx: PWM I/O CONTROL x REGISTER (CONTINUED) bit 3-2 CLDAT<1:0>: State for PWMxH and PWMxL Pins if CLMOD is Enabled bits(2) IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode: If current-limit is active, then CLDAT<1> provides the state for PWMxH. If current-limit is active, then CLDAT<0> provides the state for PWMxL. IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode: CLDAT<1:0> is ignored.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-21: FCLCONx: PWM FAULT CURRENT-LIMIT CONTROL x REGISTER R/W-0 IFLTMOD bit 15 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CLSRC<4:0>(2,3) R/W-0 FLTSRC<4:0>(2,3) bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-10 W = Writable bit ‘1’ = Bit is set R/W-0 R/W-0 R/W-0 R/W-0 FLTPOL(1) R/W-0 CLPOL(1) R/W-0 CLMOD bit 8 R/W-0 R/W-0 FLTMOD<1:0> bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unkno
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-21: FCLCONx: PWM FAULT CURRENT-LIMIT CONTROL x REGISTER (CONTINUED) bit 9 bit 8 bit 7-3 bit 2 bit 1-0 CLPOL: Current-Limit Polarity for PWM Generator # bit(1) 1 = The selected current-limit source is active-low 0 = The selected current-limit source is active-high CLMOD: Current-Limit Mode Enable for PWM Generator # bit 1 = Current-Limit mode is enabled 0 = Current-Limit mode is disabled FLTSRC<4:0>: Fault Control Signal Source Se
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-22: STRIGx: PWM SECONDARY TRIGGER x COMPARE VALUE REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STRGCMP<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STRGCMP<7:3> U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 STRGCMP<15:3>: PWM Secondary Trigge
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-23: LEBCONx: LEADING-EDGE BLANKING CONTROL x REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 PHR PHF PLR PLF FLTLEBEN CLLEBEN — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — BCH(1) BCL(1) BPHH BPHL BPLH BPLL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown b
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-24: LEBDLYx: LEADING-EDGE BLANKING DELAY x REGISTER U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 LEB<11:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEB<7:3> U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-3 LEB<11:3>
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-25: AUXCONx: PWM AUXILIARY CONTROL x REGISTER R/W-0 R/W-0 U-0 U-0 HRPDIS HRDDIS — — R/W-0 R/W-0 R/W-0 R/W-0 BLANKSEL<3:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 CHOPSEL<3:0> R/W-0 R/W-0 CHOPHEN CHOPLEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HRPDIS: High-Reso
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-26: PWMCAPx: PRIMARY PWM TIME BASE CAPTURE x REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 PWMCAP<15:8>(1,2,3,4) bit 15 bit 8 R-0 R-0 R-0 PWMCAP<7:3> R-0 R-0 (1,2,3,4) U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 PWMCAP<15:3>: Captured PWM Time Base Value bits(1,2,
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 17.0 QUADRATURE ENCODER INTERFACE (QEI) MODULE This chapter describes the Quadrature Encoder Interface (QEI) module and associated operational modes. The QEI module provides the interface to incremental encoders for obtaining mechanical position data. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 17-1: QEIxCON: QEIx CONTROL REGISTER (x = 1 or 2) R/W-0 U-0 R/W-0 R-0 R/W-0 CNTERR(1) — QEISIDL INDEX UPDN(2) R/W-0 R/W-0 R/W-0 QEIM<2:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 SWPAB PCDOUT TQGATE R/W-0 R/W-0 TQCKPS<1:0>(3) R/W-0 R/W-0 R/W-0 POSRES(4) TQCS UPDN_SRC(5) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cle
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 17-1: QEIxCON: QEIx CONTROL REGISTER (x = 1 or 2) (CONTINUED) bit 5 TQGATE: Timer Gated Time Accumulation Enable bit 1 = Timer gated time accumulation is enabled 0 = Timer gated time accumulation is disabled bit 4-3 TQCKPS<1:0>: Timer Input Clock Prescale Select bits(3) 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 2 POSRES: Position Counter Reset Enable bit(4) 1 = Index pul
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 17-2: DFLTxCON: DIGITAL FILTER x CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 IMV<2:0> CEID bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 U-0 U-0 QEOUT QECK<2:0> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 IMV<1:0>: I
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 18.0 SERIAL PERIPHERAL INTERFACE (SPI) Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/ 610 and dsPIC33FJ64GS406/606/608/ 610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 18.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 18-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 SPIEN — SPISIDL — — — — — bit 15 bit 8 U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0 — SPIROV — — — — SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx Ena
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 18-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 SSEN(3) CKP MSTEN R/W-0 R/W-0 R/W-0 R/W-0 SPRE<2:0>(2) R/W-0 PPRE<1:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 18-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(2) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(2) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: 2: 3: The CKE bit is not used in the Framed SPI modes.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 18-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — FRMDLY — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx s
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70591E-page 266 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 19.0 INTER-INTEGRATED CIRCUIT (I2C™) Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 19-1: I2C™ BLOCK DIAGRAM (X = 1 or 2) Internal Data Bus I2CxRCV SCLx Read Shift Clock I2CxRSR LSb SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSb Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 19-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ =
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 19-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HSC R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS IWCOL I2COV R-0, HSC R/C-0, HSC R/C-0, HSC D_A P R-0, HSC R-0, HSC R-0, HSC R_W RBF TBF S bit 7 bit 0 Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Hardware Settable bit HSC = Har
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 19-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 AMSK<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSK<9:0>:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70591E-page 274 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 20.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 20-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 UARTEN(1) — USIDL IREN(2) RTSMD — R/W-0 R/W-0 UEN<1:0> bit 15 bit 8 R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 WAKE LPBACK ABAUD URXINV BRGH R/W-0 R/W-0 PDSEL<1:0> R/W-0 STSEL bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 20-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 URXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd pa
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 20-2: R/W-0 UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 UTXISEL1 UTXINV R/W-0 UTXISEL0 U-0 R/W-0, HC — UTXBRK R/W-0 (1) UTXEN R-0 R-1 UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 URXISEL<1:0> R/W-0 R-1 R-0 R-0 R/C-0 R-0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HC = Hardware Clearable bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for t
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70591E-page 280 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 21.0 ENHANCED CAN (ECAN™) MODULE Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 21-1: ECANx MODULE BLOCK DIAGRAM RxF15 Filter RxF14 Filter RxF13 Filter RxF12 Filter DMA Controller RxF11 Filter RxF10 Filter RxF9 Filter RxF8 Filter TRB7 TX/RX Buffer Control Register RxF7 Filter TRB6 TX/RX Buffer Control Register RxF6 Filter TRB5 TX/RX Buffer Control Register RxF5 Filter TRB4 TX/RX Buffer Control Register RxF4 Filter TRB3 TX/RX Buffer Control Register RxF3 Filter TRB2 TX/RX Buffer Control Register RxF2 Filt
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 21.3 Modes of Operation The ECAN™ module can operate in one of several operation modes selected by the user. These modes include: • • • • • • Initialization mode Disable mode Normal Operation mode Listen Only mode Listen All Messages mode Loopback mode Modes are requested by setting the REQOP<2:0> bits (CxCTRL1<10:8>). Entry into a mode is Acknowledged by monitoring the OPMODE<2:0> bits (CxCTRL1<7:5>).
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-1: CxCTRL1: ECANx CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 r-0 — — CSIDL ABAT r R/W-1 R/W-0 R/W-0 REQOP<2:0> bit 15 bit 8 R-1 R-0 R-0 U-0 R/W-0 U-0 U-0 R/W-0 — CANCAP — — WIN OPMODE<2:0> bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-2: CxCTRL2: ECANx CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R-0 R-0 R-0 R-0 R-0 DNCNT<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 DNCNT<4:0>: DeviceNet™ Filter Bit Number bits 10010-11111 =
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-3: CxVEC: ECANx INTERRUPT CODE REGISTER U-0 U-0 U-0 — — — R-0 R-0 R-0 R-0 R-0 FILHIT<4:0> bit 15 bit 8 U-0 R-1 R-0 R-0 — R-0 R-0 R-0 R-0 ICODE<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 FILHIT<4:0>: Filter Hit Number bits 10000-11111 = Reserved 011
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-4: R/W-0 CxFCTRL: ECANx FIFO CONTROL REGISTER R/W-0 R/W-0 DMABS<2:0> U-0 U-0 U-0 U-0 U-0 — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSA<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 DMABS<2:0>: DMA Buffer Size bits 111 = Reserved 110 = 32 buffers in DMA RAM 1
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-5: CxFIFO: ECANx FIFO STATUS REGISTER U-0 U-0 — — R-0 R-0 R-0 R-0 R-0 R-0 FBP<5:0> bit 15 bit 8 U-0 U-0 — — R-0 R-0 R-0 R-0 R-0 R-0 FNRB<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FBP<5:0>: FIFO Buffer Pointer bits 011111 = RB31 buffer 011110 = RB3
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-6: CxINTF: ECANx INTERRUPT FLAG REGISTER U-0 — bit 15 U-0 — R-0 TXBO R-0 TXBP R-0 RXBP R-0 TXWAR R-0 RXWAR R-0 EWARN bit 8 R/C-0 IVRIF bit 7 R/C-0 WAKIF R/C-0 ERRIF U-0 — R/C-0 FIFOIF R/C-0 RBOVIF R/C-0 RBIF R/C-0 TBIF bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 C = Writeable, but only ‘0’ can be written to clear the
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-6: bit 1 bit 0 CxINTF: ECANx INTERRUPT FLAG REGISTER (CONTINUED) RBIF: RX Buffer Interrupt Flag bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred TBIF: TX Buffer Interrupt Flag bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70591E-page 290 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-7: CxINTE: ECANx INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 IVRIE: Inv
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-8: CxEC: ECANx TRANSMIT/RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TERRCNT<7:0> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RERRCNT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 TERRCNT<7:0>: Transmit Error Count bits bit 7-0 RERRCNT<7:0>: Receive Error Count bits REGISTER
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-10: CxCFG2: ECANx BAUD RATE CONFIGURATION REGISTER 2 U-0 R/W-x U-0 U-0 U-0 — WAKFIL — — — R/W-x R/W-x R/W-x SEG2PH<2:0> bit 15 bit 8 R/W-x R/W-x SEG2PHTS SAM R/W-x R/W-x R/W-x SEG1PH<2:0> R/W-x R/W-x R/W-x PRSEG<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemente
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-11: CxFEN1: ECANx ACCEPTANCE FILTER ENABLE REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-13: CxBUFPNT2: ECANx FILTER 4-7 BUFFER POINTER REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F7BP<3:0> R/W-0 R/W-0 R/W-0 F6BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F5BP<3:0> R/W-0 R/W-0 R/W-0 F4BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 F7BP<3:0>: RX Buffer Mask for Filter 7 bits 1
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-14: CxBUFPNT3: ECANx FILTER 8-11 BUFFER POINTER REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F11BP<3:0> R/W-0 R/W-0 R/W-0 F10BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F9BP<3:0> R/W-0 R/W-0 R/W-0 F8BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F11BP<3:0>: RX Buffer
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-15: CxBUFPNT4: ECANx FILTER 12-15 BUFFER POINTER REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F15BP<3:0> R/W-0 R/W-0 R/W-0 F14BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F13BP<3:0> R/W-0 R/W-0 R/W-0 F12BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F15BP<3:0>: RX Buff
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-16: CxRXFnSID: ECANx ACCEPTANCE FILTER n STANDARD IDENTIFIER REGISTER (n = 0-15) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 15 bit 8 R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-17: CxRXFnEID: ECANx ACCEPTANCE FILTER n EXTENDED IDENTIFIER REGISTER (n = 0-15) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is se
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-19: CxFMSKSEL2: ECANx FILTER 15-8 MASK SELECTION REGISTER 2 R/W-0 R/W-0 F15MSK<1:0> R/W-0 R/W-0 R/W-0 F14MSK<1:0> R/W-0 R/W-0 F13MSK<1:0> R/W-0 F12MSK<1:0> bit 15 bit 8 R/W-0 R/W-0 F11MSK<1:0> R/W-0 R/W-0 R/W-0 F10MSK<1:0> R/W-0 R/W-0 F9MSK<1:0> R/W-0 F8MSK<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-20: CxRXMnSID: ECANx ACCEPTANCE FILTER MASK n STANDARD IDENTIFIER REGISTER (n = 0-2) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 15 bit 8 R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — MIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ =
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-22: CxRXFUL1: ECANx RECEIVE BUFFER FULL REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 bit 7 bit 0 Legend: C = Writeable, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Un
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-24: CxRXOVF1: ECANx RECEIVE BUFFER OVERFLOW REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 bit 7 bit 0 Legend: C = Writeable, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-26: CxTRmnCON: ECANx TX/RX BUFFER mn CONTROL REGISTER (m = 0, 2, 4, 6; n = 1, 3, 5, 7) R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 TXENn TXABTn TXLARBn TXERRn TXREQn RTRENn R/W-0 R/W-0 TXnPRI<1:0> bit 15 bit 8 R/W-0 R-0 TXENm TXABTm(1) R-0 R-0 (1) TXLARBm TXERRm (1) R/W-0 R/W-0 TXREQm RTRENm R/W-0 R/W-0 TXmPRI<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Val
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 21.4 ECANx Message Buffers ECANx message buffers are part of DMA RAM memory. They are not ECAN Special Function Registers. The user application must directly write into the DMA RAM area that is configured for ECANx message buffers. The location and size of the buffer area is defined by the user application.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 ( BUFFER 21-3: ECANx MESSAGE BUFFER WORD 2 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID5 EID4 EID3 EID2 EID1 EID0 RTR RB1 bit 15 bit 8 U-x U-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x — — — RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 EID<5:0>: Extended Identifier bits
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 BUFFER 21-5: R/W-x ECANx MESSAGE BUFFER WORD 4 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 3 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Byte 3<15:8>: ECANx Message Byte 3 bit 7-0 Byte 2<7:0>: ECANx Message Byte 2 BUFFER 21-6: R/W-x x = B
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 BUFFER 21-7: R/W-x ECANx MESSAGE BUFFER WORD 6 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 7 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 6 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Byte 7<15:8>: ECANx Message Byte 7 bit 7-0 Byte 6<7:0>: ECANx Message Byte 6 BUFFER 21-8: x = Bit is
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 22.0 HIGH-SPEED, 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 44.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 22.3 Module Functionality The High-Speed, 10-Bit ADC is designed to support power conversion applications when used with the High-Speed PWM module. The ADC may have one or two SAR modules, depending on the device variant. If two SARs are present on a device, two conversions can be processed at a time, yielding 4 Msps conversion rate.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 22-1: ADC BLOCK DIAGRAM FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 AN4 Eight 16-Bit Registers Bus Interface SAR Core Data Format AN2 AN6 AN1 Shared Sample and Hold AN3 AN5 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 22-2: ADC BLOCK DIAGRAM FOR dsPIC33FJ32GS606 AND dsPIC33FJ64GS606 DEVICES WITH TWO SARS Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 Data Format SAR Core Seven 16-Bit Registers Data Format AN2 Seven 16-Bit Registers AN4 AN6 Even Numbered Inputs with Shared S&H Bus Interface AN8 AN10 AN12 AN14 AN24(1) (EXTREF) Odd Numbered Inputs with Shared S&H AN1 SAR Core AN3 AN5 AN9 AN11 AN13 AN15 AN25(2) (
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 22-3: ADC BLOCK DIAGRAM FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES WITH TWO SARS Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 Data Format SAR Core Seven 16-Bit Registers Data Format AN2 Seven 16-Bit Registers AN4 AN6 Even Numbered Inputs with Shared S&H Bus Interface AN8 AN10 AN12 AN14 AN16 AN24(1) (EXTREF) Odd Numbered Inputs with Shared S&H AN1 SAR Core AN3 AN5 AN7 AN9 AN11 AN13 AN15 AN
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 22-4: ADC BLOCK DIAGRAM FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES WITH TWO SARS Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 Data Format SAR Core Seven 16-Bit Registers Data Format AN2 Seven 16-Bit Registers AN4 AN6 Even Numbered Inputs with Shared S&H Bus Interface AN8 AN10 AN12 AN14 AN16 AN18 AN20 AN22 AN24(1) (EXTREF) AN1 Odd Numbered Inputs with Shared S&H SAR Core AN3 AN5 AN7 AN9 AN11
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-1: ADCON: ADC CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 ADON — ADSIDL SLOWCLK(1) — GSWTRG — FORM(1) bit 15 bit 8 R/W-0 EIE(1) R/W-0 R/W-0 R/W-0 U-0 ORDER(1,2) SEQSAMP(1,2) ASYNCSAMP(1) R/W-0 — R/W-1 R/W-1 ADCS<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-1: ADCON: ADC CONTROL REGISTER (CONTINUED) bit 3 Unimplemented: Read as ‘0’ bit 2-0 ADCS<2:0>: Analog-to-Digital Conversion Clock Divider Select bits(1) 111 = FADC/8 110 = FADC/7 101 = FADC/6 100 = FADC/5 011 = FADC/4 (default) 010 = FADC/3 001 = FADC/2 000 = FADC/1 Note 1: 2: This control bit can only be changed while the ADC is disabled (ADON = 0). This control bit is only active on devices that have one SAR.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-2: U-0 ADSTAT: ADC STATUS REGISTER U-0 — U-0 — — R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS (1) (1) (1) (1) P8RDY(1) P12RDY P11RDY P10RDY P9RDY bit 15 bit 8 R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS P7RDY(1) (1) (1) (1) (1) (1) (1) P0RDY(1) P6RDY P5RDY P4RDY P3RDY P2RDY P1RDY bit 7 bit 0 Legend: C = Clearable bit HS - Hardware Settable bit R
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-3: R/W-0 ADBASE: ADC BASE REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADBASE<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADBASE<7:1> U-0 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 ADBASE<15:1>: ADC Base Address bits This register contains the base
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-4: R/W-0 ADPCFG: ADC PORT CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG<15:8>(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG<7:0> R/W-0 R/W-0 R/W-0 (1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: x = Bit is unknown PCFG<15:0>: ADC Port Configuration Control bit
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-6: ADCPC0: ADC CONVERT PAIR CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 IRQEN1 PEND1 SWTRG1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC1<4:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 IRQEN0 PEND0 SWTRG0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC0<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IRQEN1:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-6: ADCPC0: ADC CONVERT PAIR CONTROL REGISTER 0 (CONTINUED) bit 12-8 TRGSRC1<4:0>: Trigger 1 Source Selection bits Selects trigger source for conversion of Analog Channels AN3 and AN2.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-6: bit 4-0 Note 1: ADCPC0: ADC CONVERT PAIR CONTROL REGISTER 0 (CONTINUED) TRGSRC0<4:0>: Trigger 0 Source Selection bits Selects trigger source for conversion of Analog Channels AN1 and AN0.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-7: ADCPC1: ADC CONVERT PAIR CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 IRQEN3 PEND3 SWTRG3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC3<4:0>(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 IRQEN2 PEND2 SWTRG2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC2<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IRQE
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-7: ADCPC1: ADC CONVERT PAIR CONTROL REGISTER 1 (CONTINUED) bit 12-8 TRGSRC3<4:0>: Trigger 3 Source Selection bits(1) Selects trigger source for conversion of analog channels AN7 and AN6.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-7: bit 4-0 Note 1: ADCPC1: ADC CONVERT PAIR CONTROL REGISTER 1 (CONTINUED) TRGSRC2<4:0>: Trigger 2 Source Selection bits Selects trigger source for conversion of Analog Channels AN5 and AN4.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-8: ADCPC2: ADC CONVERT PAIR CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 IRQEN5 PEND5 SWTRG5 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC5<4:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 IRQEN4 PEND4 SWTRG4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC4<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IRQEN5:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-8: ADCPC2: ADC CONVERT PAIR CONTROL REGISTER 2 (CONTINUED) bit 12-8 TRGSRC5<4:0>: Trigger 5 Source Selection bits Selects trigger source for conversion of Analog Channels AN11 and AN10.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-8: bit 4-0 Note 1: ADCPC2: ADC CONVERT PAIR CONTROL REGISTER 2 (CONTINUED) TRGSRC4<4:0>: Trigger 4 Source Selection bits Selects trigger source for conversion of Analog Channels AN9 and AN8.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-9: ADCPC3: ADC CONVERT PAIR CONTROL REGISTER 3 R/W-0 R/W-0 R/W-0 IRQEN7 PEND7 SWTRG7 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC7<4:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 IRQEN6 PEND6 SWTRG6 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC6<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IRQEN7:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-9: ADCPC3: ADC CONVERT PAIR CONTROL REGISTER 3 (CONTINUED) bit 12-8 TRGSRC7<4:0>: Trigger 7 Source Selection bits Selects trigger source for conversion of Analog Channels AN15 and 14.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-9: bit 4-0 Note 1: ADCPC3: ADC CONVERT PAIR CONTROL REGISTER 3 (CONTINUED) TRGSRC6<4:0>: Trigger 6 Source Selection bits Selects trigger source for conversion of Analog Channels AN13 and AN12.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-10: ADCPC4: ADC CONVERT PAIR CONTROL REGISTER 4 R/W-0 R/W-0 R/W-0 IRQEN9 PEND9 SWTRG9 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC9<4:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 IRQEN8 PEND8 SWTRG8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC8<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IRQEN9:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-10: ADCPC4: ADC CONVERT PAIR CONTROL REGISTER 4 (CONTINUED) bit 12-8 TRGSRC9<4:0>: Trigger 9 Source Selection bits Selects trigger source for conversion of analog channels AN19 and AN18.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-10: ADCPC4: ADC CONVERT PAIR CONTROL REGISTER 4 (CONTINUED) bit 4-0 Note 1: TRGSRC8<4:0>: Trigger 8 Source Selection bits Selects trigger source for conversion of Analog Channels AN17 and AN16.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-11: ADCPC5: ADC CONVERT PAIR CONTROL REGISTER 5 R/W-0 R/W-0 R/W-0 IRQEN11 PEND11 SWTRG11 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC11<4:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 IRQEN10 PEND10 SWTRG10 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC10<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-11: ADCPC5: ADC CONVERT PAIR CONTROL REGISTER 5 (CONTINUED) bit 12-8 TRGSRC11<4:0>: Trigger 11 Source Selection bits Selects trigger source for conversion of analog channels AN23 and AN22.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-11: ADCPC5: ADC CONVERT PAIR CONTROL REGISTER 5 (CONTINUED) bit 4-0 Note 1: TRGSRC10<4:0>: Trigger 10 Source Selection bits Selects trigger source for conversion of analog channels AN21 and AN20.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-12: ADCPC6: ADC CONVERT PAIR CONTROL REGISTER 6(2) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 IRQEN12 PEND12 SWTRG12 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC12<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-12: ADCPC6: ADC CONVERT PAIR CONTROL REGISTER 6(2) (CONTINUED) bit 4-0 TRGSRC12<4:0>: Trigger 12 Source Selection bits Selects trigger source for conversion of analog channels AN25 and AN24.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70591E-page 340 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 23.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 23.3 Module Applications 23.5 Interaction with I/O Buffers This module provides a means for the SMPS dsPIC® DSC devices to monitor voltage and currents in a power conversion application. The ability to detect transient conditions and stimulate the dsPIC DSC processor and/or peripherals, without requiring the processor and ADC to constantly monitor voltages or currents, frees the dsPIC DSC to perform other tasks.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 23-1: CMPCONx: COMPARATOR CONTROL x REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 CMPON — CMPSIDL r r r r DACOE bit 15 bit 8 R/W-0 R/W-0 INSEL<1:0> R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 EXTREF r CMPSTAT r CMPPOL RANGE bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown b
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 23-2: CMPDACx: COMPARATOR DAC CONTROL x REGISTER U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 CMREF<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CMREF<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Reserved: Read as ‘0’ bit 9-0 CMREF<9:0>: Compar
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 24.0 SPECIAL FEATURES 24.1 Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest “dsPIC33F/PIC24H Family Reference Manual” sections.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 24-2: dsPIC33F CONFIGURATION BITS DESCRIPTION Bit Field Register RTSP Effect BWRP FBS Immediate Boot Segment Program Flash Write Protection bit 1 = Boot segment can be written 0 = Boot segment is write-protected BSS<2:0> FBS Immediate Boot Segment Program Flash Code Protection Size bits X11 = No boot program Flash segment Boot space is 256 instruction words (except interrupt vectors) 110 = Standard security; boot program Flash s
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 24-2: Bit Field dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED) Register RTSP Effect Description FWDTEN FWDT Immediate Watchdog Timer Enable bit 1 = Watchdog Timer is always enabled (LPRC oscillator cannot be disabled; clearing the SWDTEN bit in the RCON register will have no effect) 0 = Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register) WINDIS FWDT Immedi
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 24-2: dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register RTSP Effect Description CMPPOL1 FCMP Immediate Comparator Hysteresis Polarity bit (for odd numbered comparators) 1 = Hysteresis is applied to falling edge 0 = Hysteresis is applied to rising edge HYST1<1:0> FCMP Immediate Comparator Hysteresis Select bits 11 = 45 mV hysteresis 10 = 30 mV hysteresis 01 = 15 mV hysteresis 00 = No hysteresis DS70591E-pag
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 24.2 On-Chip Voltage Regulator 24.3 Brown-out Reset (BOR) The dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices power their core digital logic at a nominal 2.5V. This can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3V.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 The WDT, prescaler and postscaler are reset: 24.4.3 • On any device Reset • On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits) or by hardware (i.e., Fail-Safe Clock Monitor) • When a PWRSAV instruction is executed (i.e.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 24.5 JTAG Interface 24.7 In-Circuit Debugger dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices implement a JTAG interface, which supports boundary scan device testing, as well as in-circuit programming. Detailed information on this interface will be provided in future revisions of the document. When MPLAB ICD 3 is selected as a debugger, the incircuit debugging functionality is enabled.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 24.8 Code Protection and CodeGuard™ Security The code protection features are controlled by the Configuration registers: FBS and FGS. The dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices offer the intermediate implementation of CodeGuard™ Security. CodeGuard Security enables multiple parties to securely share resources (memory, interrupts and peripherals) on a single chip.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 25.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest “dsPIC33F/PIC24H Family Reference Manual” sections.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Most instructions are a single word. Certain double-word instructions are designed to provide all the required information in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. The double-word instructions execute in two instruction cycles.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 25-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm*Wm Multiplicand and Multiplier Working register pair for Square instructions {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier Working register pair for DSP instructions {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 Working registers {W0..W15} Wnd One of 16 Destination Working registers {W0...
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 25-2: Base Instr # 1 2 3 4 INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR Assembly Syntax # of # of Words Cycles Description Status Flags Affected ADD Acc Add Accumulators 1 1 ADD f f = f + WREG 1 1 OA,OB,SA,SB C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 25-2: Base Instr # 9 10 11 12 13 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTG BTSC BTSS BTST BTSTS Assembly Syntax Description # of # of Words Cycles Status Flags Affected BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3) None BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3) None BTSS f,#bit4 Bit Test f, Skip if
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 25-2: Base Instr # 29 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic DIV Assembly Syntax # of # of Words Cycles Description Status Flags Affected DIV.S Wm,Wn Signed 16/16-Bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-Bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-Bit Integer Divide 1 18 N,Z,C,OV DIV.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 25-2: Base Instr # 48 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic MPY Assembly Syntax Description # of # of Words Cycles Status Flags Affected MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 49 MPY.N MPY.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 25-2: Base Instr # 66 67 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic RRNC SAC Assembly Syntax # of # of Words Cycles Description Status Flags Affected RRNC f f = Rotate Right (No Carry) f 1 1 RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 26.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 26.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 26.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 26.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 26.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 27.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 family are listed below.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 27.1 DC Characteristics TABLE 27-1: OPERATING MIPS vs. VOLTAGE Max MIPS Characteristic VDD Range (in Volts) — 3.0-3.6V(1) -40°C to +85°C 40 — 3.0-3.6V(1) -40°C to +125°C 40 Note 1: Temp Range (in °C) dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules, such as the ADC, etc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions Operating Voltage DC10 VDD Supply Voltage(4) 3.0 — 3.6 V DC12 VDR RAM Data Retention Voltage(2) 1.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter Typical(1) No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter Typical(1) No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Typ(1) Max Units Conditions Input Low Voltage DI10 I/O Pins VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 I/O Pins with OSC1 or SOSCI VSS — 0.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param Symbol No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions Program Flash Memory D130 EP Cell Endurance 10,000 — — E/W D131 VPR VDD for Read VMIN — 3.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 27.2 AC Characteristics and Timing Parameters This section defines dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 AC characteristics and timing parameters. TABLE 27-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Operating voltage VDD range as described in Section 27.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 OS30 OS30 Q3 Q4 OSC1 OS20 OS31 OS31 OS25 CLKO OS41 OS40 TABLE 27-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol OS50 OS51 Characteristic Min Typ(1) Max Units FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range 0.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-19: AC CHARACTERISTICS: INTERNAL FRC ACCURACY AC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for Extended Min Typ Max Units Conditions Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1) F20a FRC -1 — +1 % -40°C TA +85°C VDD = 3.0-3.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 27-1 for load conditions. TABLE 27-21: I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-4: VDD RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 MCLR SY10 Internal POR PWRT Time-out OSC Time-out SY11 SY30 Internal Reset Watchdog Timer Reset SY13 SY20 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 27-1 for load conditions. 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-5: TIMER1/2/3 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 OS60 Tx20 TMRx Note: Refer to Figure 27-1 for load conditions. TABLE 27-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-24: TIMER2/4 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-6: INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure 27-1 for load conditions. TABLE 27-26: INPUT CAPTURE x TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-8: OUTPUT COMPARE x/PWMx MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 OCx Tri-state Active TABLE 27-28: SIMPLE OCx/PWMx MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-9: HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS MP30 FLTx MP20 PWMx FIGURE 27-10: HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure 27-1 for load conditions. TABLE 27-29: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-30: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-31: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-13: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP30, SP31 SP40 SDIx LSb MSb In LSb In Bit 14 - - - -1 SP41 Note: Refer to Figure 27-1 for load conditions. TABLE 27-32: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-14: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 SP30, SP31 SDIx MSb In LSb SP30, SP31 LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 27-1 for load conditions. TABLE 27-33: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-15: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 27-1 for load conditions. DS70591E-page 394 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-16: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 SP52 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 27-1 for load conditions. DS70591E-page 396 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-17: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 27-1 for load conditions. DS70591E-page 398 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-18: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 27-1 for load conditions. DS70591E-page 400 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-37: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-19: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 27-1 for load conditions. FIGURE 27-20: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 27-1 for load conditions.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-38: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-21: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition FIGURE 27-22: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out DS70591E-page 404 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-39: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-40: 10-BIT, HIGH-SPEED ADC MODULE SPECIFICATIONS Standard Operating Conditions: 3.0V and 3.6V(2) (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min Typ Max Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of VDD – 0.3 or 3.0 — Lesser of VDD + 0.3 or 3.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-41: 10-BIT, HIGH-SPEED ADC MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V(2) (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units — ns Conditions Clock Parameters AD50b TAD ADC Clock Period AD55b tCONV Conversion Time AD56b FCNV Throughput Rate 35.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-42: COMPARATOR MODULE SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature: -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC and DC CHARACTERISTICS Param. Symbol Characteristic No. Min Typ Max Units CM10 VIOFF Input Offset Voltage ±5 ±15 mV CM11 VICM Input Common-Mode Voltage Range(1) 0 — AVDD – 1.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-44: DAC OUTPUT BUFFER SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature: -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. Symbol Characteristic No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-45: QUADRATURE DECODER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-46: QEI INDEX PULSE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-27: ECAN™ MODULE I/O TIMING CHARACTERISTICS CxTx Pin (output) New Value Old Value CA10 CA11 CxRx Pin (input) CA20 TABLE 27-48: ECAN™ MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 28.0 50 MIPS ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 electrical characteristics for devices operating at 50 MIPS. Specifications are identical to those shown in Section 27.0 “Electrical Characteristics”, with the exception of the parameters listed in this section.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 28.1 DC Characteristics TABLE 28-1: OPERATING MIPS vs. VOLTAGE Characteristic VDD Range (in Volts) Temp Range (in °C) — 3.0-3.6V(1) -40°C to +85°C Note 1: Max MIPS dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 50 Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 28-3: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical Max Units Conditions Idle Current (IIDLE): Core Off Clock On Base Current(1) MDC45d 40 50 mA -40°C MDC45a 40 50 mA +25°C MDC45b 40 50 mA +85°C Note 1: 3.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 28-4: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Parameter No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 28.2 AC Characteristics and Timing Parameters This section defines the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 AC characteristics and timing parameters for 50 MIPS devices. TABLE 28-5: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 28-6: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 28-7: TIMER2/4 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param No.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 28-9: SIMPLE OCx/PWMx MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param No.
DC AND AC DEVICE CHARACTERISTICS GRAPHS Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. FIGURE 29-1: VOH – 4x DRIVER PINS -0.080 -0.030 3.6V -0.
FIGURE 29-6: VOL – 4x DRIVER PINS 0.120 0.040 0.035 3.6V 0.030 3.6V 0.100 3.3V 0.025 3.3V 0.080 3V IOL (A) IOL (A) VOL – 16x DRIVER PINS 0.020 0.015 Absolute Maximum 3V 0.060 Absolute Maximum 0.040 0.010 0.020 0.005 0.000 0.00 1.00 2.00 3.00 4.00 VOL (V) FIGURE 29-5: 0.060 3.6V 0.050 3.3V IOL (A) 2009-2012 Microchip Technology Inc. 3V 0.030 Absolute Maximum 0.020 0.010 0.000 0.00 1.00 2.00 VOL (V) 1.00 2.00 VOL (V) VOL – 8x DRIVER PINS 0.040 0.000 0.00 3.00 4.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 30.0 PACKAGING INFORMATION 30.1 Package Marking Information 64-Lead QFN (9x9x0.9mm) XXXXXXXXXX XXXXXXXXXX YYWWNNN 64-Lead TQFP (10x10x1mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 80-Lead TQFP (12x12x1mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 30.1 Package Marking Information (Continued) 100-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 100-Lead TQFP (14x14x1mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN DS70591E-page 424 Example dsPIC33FJ64 GS608-I/PT e3 1210017 Example 33FJ32GS610 -I/PF e3 1210017 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 30.2 Package Details Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70591E-page 426 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 E e E1 N b NOTE 1 123 NOTE 2 α A φ c A2 β A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 E e E1 N b NOTE 1 12 3 α NOTE 2 A c β φ A2 A1 L1 L 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 e E E1 N b NOTE 1 1 23 NOTE 2 α c A φ L β A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV A2 L1 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 3) ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 e E1 E b N α NOTE 1 1 23 A NOTE 2 φ c β A2 A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70591E-page 436 2009-2012 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 APPENDIX A: MIGRATING FROM dsPIC33FJ06GS101/X02 AND dsPIC33FJ16GSX02/X04 TO dsPIC33FJ32GS406/606/608/610 AND dsPIC33FJ64GS406/606/608/610 DEVICES This appendix provides an overview of considerations for migrating from the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 family of devices to the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 family of devices.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 APPENDIX B: REVISION HISTORY Revision B (November 2009) The revision includes the following global update: Revision A (March 2009) • Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits This is the initial release of this document.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE B-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section 9.0 “Oscillator Configuration” Removed Section 9.2 “FRC Tuning”. Removed the PRCDEN, TSEQEN, and LPOSCEN bits from the Oscillator Control Register (see Register 9-1). Updated the Oscillator Tuning Register (see Register 9-4). Removed the Oscillator Tuning Register 2 and the Linear Feedback Shift Register.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE B-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 27.0 “Electrical Characteristics” Update Description Updated the Absolute Maximum Ratings for high temperature and added Note 4. Updated all Operating Current (IDD) Typical and Max values in Table 27-5. Updated all Idle Current (IIDLE) Typical and Max values in Table 27-6. Updated all Power-Down Current (IPD) Typical and Max values in Table 27-7.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Revision C (February 2010) This revision includes minor typographical and formatting changes throughout the data sheet text. All other changes are referenced by their respective section in Table B-2. TABLE B-2: MAJOR SECTION UPDATES Section Name Section 16.0 “High-Speed PWM” Update Description Added Note 2 to PTPER (Register 16-3). Added Note 1 to SEVTCMP (Register 16-4). Updated Note 1 in MDC (Register 16-10).
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Revision D (January 2012) This revision includes minor typographical and formatting changes throughout the data sheet text. All other changes are referenced by their respective section in Table B-3. All occurrences of PGCn and PGDn (where n = 1, 2, or 3) were updated to: PGECn and PGEDn throughout the document.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE B-3: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section 23.0 “High-Speed Analog Comparator” Added Note 1 to the High-Speed Analog Comparator Module block diagram (see Figure 23-1). Section 24.0 “Special Features” Updated Section 24.1 “Configuration Bits”. Added the RTSP Effect column to the dsPIC33F Configuration Bits Description (see Table 24-2).
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE B-3: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 27.0 “Electrical Characteristics” (Continued) Update Description Updated the Timer1, Timer2, and Timer3 External Clock Timing Requirements (see Table 27-23, Table 27-24, and Table 27-25). Updated the Simple OC/PWM Mode Timing Requirements (see Table 27-28). Updated all SPI Timing specifications (see Figure 27-11-Figure 27-18 and Table 27-30-Table 27-37).
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 INDEX A C AC Characteristics ............................................................ 378 10-Bit, High-Speed ADC ........................................... 406 Internal FRC Accuracy.............................................. 381 Internal LPRC Accuracy............................................ 381 Load Conditions ........................................................ 378 Temperature and Voltage Specifications ..................
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 DC Characteristics (50 MIPS) Doze Current (IDOZE) ................................................ 416 Idle Current (IIDLE) .................................................... 415 Operating Current (IDD)............................................. 414 Operating MIPS vs. Voltage...................................... 414 Development Support .......................................................
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 L Leading-Edge Blanking (LEB)........................................... 229 LPRC Oscillator Use with WDT ........................................................... 349 M Memory Organization.......................................................... 45 Microchip Internet Web Site ..............................................
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Interrupt Controller (dsPIC33FJ64GS608 Devices)........................... 57 Interrupt Controller (dsPIC33FJ64GS610 Devices)........................... 55 NVM ............................................................................ 96 Output Compare ......................................................... 70 PMD (dsIPC33FJ64GS606 Devices) .......................... 97 PMD (dsPIC33FJ32GS406 and dsPIC33FJ64GS406 Devices) .....................
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 IEC5 (Interrupt Enable Control 5) ............................. 147 IEC6 (Interrupt Enable Control 6) ............................. 148 IEC7 (Interrupt Enable Control 7) ............................. 149 IFS0 (Interrupt Flag Status 0) ................................... 132 IFS1 (Interrupt Flag Status 1) ................................... 134 IFS2 (Interrupt Flag Status 2) ................................... 135 IFS3 (Interrupt Flag Status 3) ..
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 404 Input Capture x (ICx)................................................. 387 OCx/PWMx ............................................................... 388 Output Compare Operation....................................... 226 Output Compare x (OCx) .......................................... 387 QEA/QEB Input .........................................................
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 32 GS4 06 T - 50 I / PT - XXX Examples: a) dsPIC33FJ32GS406-50I/PT: SMPS dsPIC33, 32-Kbyte program memory, 64-pin, 50 MIPS, Industrial temp., TQFP package.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70591E-page 454 2009-2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.