Datasheet

© 2007-2012 Microchip Technology Inc. DS70292G-page 309
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
26.2 PMP Control Registers
REGISTER 26-1: PMCON: PARALLEL MASTER PORT CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMPEN
— PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0
(1)
U-0 R/W-0
(1)
R/W-0 R/W-0 R/W-0
CSF1 CSF0 ALP
— CS1P BEP WRSP RDSP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PMPEN: Parallel Master Port Enable bit
1 = PMP enabled
0 = PMP disabled, no off-chip access performed
bit 14 Unimplemented: Read as ‘0’
bit 13 PSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-11 ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits
(1)
11 = Reserved
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 3 bits are multiplexed on
PMA<10:8>
00 = Address and data appear on separate pins
bit 10 PTBEEN: Byte Enable Port Enable bit (16-bit Master mode)
1 = PMBE port enabled
0 = PMBE port disabled
bit 9 PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port enabled
0 = PMWR/PMENB port disabled
bit 8 PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR
port enabled
0 = PMRD/PMWR
port disabled
bit 7-6 CSF1:CSF0: Chip Select Function bits
11 = Reserved
10 = PMCS1 functions as chip select
0x = PMCS1 functions as address bit 14
bit 5 ALP: Address Latch Polarity bit
(1)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL
and PMALH)
bit 4 Unimplemented: Read as ‘0’
bit 3 CS1P: Chip Select 1 Polarity bit
(1)
1 = Active-high (PMCS1/PMCS1)
0 = Active-low (PMCS1
/PMCS1)
Note 1: These bits have no effect when their corresponding pins are used as address lines.