Datasheet

© 2007-2012 Microchip Technology Inc. DS70292G-page 139
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 8-9: DSADR: MOST RECENT DMA RAM ADDRESS
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DSADR<15:8>
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DSADR<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits